Integrated chip and manufacturing method therefor, and full-color integrated chip and display panel
US-12183868-B2 · Dec 31, 2024 · US
US8962397B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8962397-B2 |
| Application number | US-201213554890-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 20, 2012 |
| Priority date | Jul 25, 2011 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.
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What is claimed is: 1. A method for fabricating a high voltage (HV) metal oxide semiconductor (MOS) field effect transistor (FET) device, said method comprising the steps of: forming a zero layer ( 222 ) on a P-substrate ( 202 ) by etching an alignment target ( 220 ) on a surface of the P-substrate ( 202 ) and outside of active device areas of the P-substrate ( 202 ); forming a lightly doped N-well ( 204 a ) in a portion of the P-substrate ( 202 ) by implant; forming a doped…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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