Systems and methods of testing memory devices
US-2024387303-A1 · Nov 21, 2024 · US
US8962354B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8962354-B2 |
| Application number | US-201414491407-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 19, 2014 |
| Priority date | Dec 6, 2012 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.
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What is claimed is: 1. A method of forming multiple samples on a substrate using high productivity combinatorial processes, the method comprising: defining a plurality of site-isolated regions on the substrate, forming a first layer in a first set of site-isolated regions of the plurality of site-isolated regions, wherein the first layer is formed using physical vapor deposition; forming a second layer in a second set of site-isolated regions of the plurality of site-isolat…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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