Memory system and memory controller

Patent metadata

Field	Value
Publication number	US-8959415-B2
Application number	US-201113237418-A
Country	US
Kind code	B2
Filing date	Sep 20, 2011
Priority date	Dec 8, 2010
Publication date	Feb 17, 2015
Grant date	Feb 17, 2015

Abstract

A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to read/write data at every page; and a memory controller operative to control the memory device. The memory controller includes a page buffer operative to hold page data to be read from/written in a page of the memory device and send/receive the page data to/from the memory device, a data processing unit operative to detect and correct an error in the page data by processing target data in a finite field Zp modulo p generated based on the page data (p is a prime that satisfies 2<p<2 d ), and a mapping unit operative to execute mapping of the target data from the data processing unit as page data within the page buffer.

First claim

What is claimed is:

1. A memory controller for controlling a memory device, said memory device including plural memory cells capable of storing d bits of data, said d being an integer of 2 or more, in accordance with plural physical quantity levels and operative to read/write data at every page composed of specific bits in certain ones of said plural memory cells,
wherein said memory controller, after reading data by said memory device, receives d pages at a time of page data stor…

Assignees

• Toda Haruki
• Toshiba Kk

Inventors

• Toda Haruki

Classifications

• G11C29/52

  Physics · mapped topic

• G06F11/1016

  Physics · mapped topic

• G11C11/56

  Physics · mapped topic

• G06F11/1072 Primary

  Physics · mapped topic