Multi-stack nanosheet structure including semiconductor device
US-2024023326-A1 · Jan 18, 2024 · US
US8957482B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8957482-B2 |
| Application number | US-73132510-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 25, 2010 |
| Priority date | Mar 31, 2009 |
| Publication date | Feb 17, 2015 |
| Grant date | Feb 17, 2015 |
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Official abstract text for this publication.
In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.
Opening claim text (preview).
What is claimed is: 1. An electrical fuse comprising: a conductive layer; a fin region that is part of a semiconductor fin structure, is below and in contact with the conductive layer, and includes a first region having a first dopant conductivity; a second region having a second dopant conductivity; and a junction between the first region and the second region; a first contact region disposed over the first region and coupled to a first side of the conductive layer; an…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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