Address generation in a data processing apparatus

Patent metadata

Field	Value
Publication number	US-8954711-B2
Application number	US-201213361229-A
Country	US
Kind code	B2
Filing date	Jan 30, 2012
Priority date	Mar 7, 2011
Publication date	Feb 10, 2015
Grant date	Feb 10, 2015

Abstract

A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

First claim

We claim:

1. A data processing apparatus comprising:
processing circuitry for processing data;
an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said data processing;
wherein said program instructions comprise an address calculating instruction having an instruction size, said processing circuitry being responsive to said address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value, wherein said processing circuitry is configured to calculate a full address specifying a memory location of an information entity from said partial address result using at least one supplementary program instruction and wherein said partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction, wherein said program instructions comprise said at least one supplementary program instruction such that said full address is obtained by execution of a set comprising at least two program instructions comprising said address calculating instruction and said at least one supplementary program instruction, wherein said full address is specified by a full offset value and said non-fixed reference address and wherein said at least one supplementary instruction provides a supplementary offset value such that said partial offset value and said supplementary offset value together specify said full offset value.

2. The data processing apparatus as claimed in claim 1 , wherein said supplementary offset value is encoded within at least one supplementary offset field of said at least one further instruction.

3. The data processing apparatus as claimed in claim 1 , wherein said partial offset value forms a first portion of said full offset value and wherein said supplementary offset value forms a further portion of said full offset value.

4. The data processing apparatus as claimed in claim 1 , wherein a bit-width of said full offset value is greater than or equal to said instruction size.

5. The data processing apparatus as claimed in claim 2 , wherein said full offset value is a 33-bit signed offset and said instruction size is 32 bits.

6. The data processing apparatus as claimed in claim 1 , wherein said data processing apparatus has access to a virtual address space having a plurality of memory frames of predetermined frame size and wherein said partial offset value is a frame offset value specifying relative to said non-fixed reference address a frame base address for a frame containing said information entity.

7. The data processing apparatus as claimed in claim 6 , wherein said partial offset value is obtained from said encoding in said at least one partial offset field and has a bit-width greater than a combined bit-width of said at least one partial offset field.

8. The data processing apparatus as claimed in claim 7 , wherein said partial offset value comprises said encoding in said at least one partial offset field and a predetermined bit-width of zeros.

9. The data processing apparatus as claimed in claim 6 , wherein said predetermined frame size corresponds to a number of bytes that is 2 F where F is the number of intra-frame offset bits and wherein said frame base address is at a predetermined offset within said frame.

10. The data processing apparatus as claimed in claim 9 , wherein said address calculating operation comprises:
(i) deriving said frame offset value from at least one field of said address calculating instruction encoding said partial offset value;
(ii) generating said partial address result comprising said frame base address.

11. The data processing apparatus as claimed in claim 10 , wherein
said at least one supplementary program instruction comprises at least one intra-frame offset field specifying an intra-frame offset value, said intra-frame offset value specifying relative to said frame base address, a location of said information entity within said frame of memory and wherein upon execution of said at least one supplementary instruction, said intra-frame offset value is combined with said frame base address result to generate said full address.

12. The data processing apparatus as claimed in claim 1 , wherein said at least one supplementary program instruction comprises one of an add instruction, and a memory access instruction.

13. The data processing apparatus as claimed in claim 11 , wherein said data processing apparatus is configured to execute a sequence of program instructions comprising said address calculating instruction and said at least one supplementary program instruction and wherein said at least one supplementary program instruction is executed subsequently to execution of said address calculating instruction but following execution of one or more intervening program instructions.

14. The data processing apparatus as claimed in claim 11 , wherein said data processing apparatus is configured to execute a sequence of program instructions comprising a plurality of instances of said address calculating instruction, each of said plurality of instances providing said partial address result of said information entity.

15. The data processing apparatus as claimed in claim 1 , wherein said address calculating instruction has an instruction bit-width and said full address has a full address bit-width different from said instruction bit-width.

16. The data processing apparatus as claimed in claim 15 , wherein said data processing apparatus has access to a virtual address space having a plurality of memory frames of predetermined frame size and wherein said partial offset value is a frame offset value specifying relative to said non-fixed reference address a frame base address for a frame containing said information entity and wherein said at least one frame offset field has a first bit-width and wherein said frame offset value has a second bit-width greater than said first bit-width.

17. The data processing apparatus as claimed in claim 16 , wherein said frame offset value is generated by combining contents of said at least one frame offset field and performing a scaling operation depending upon said predetermined frame size.

18. The data processing apparatus as claimed in 17 , wherein said full address bit-width is different from said second bit-width associated with said frame offset value.

19. The data processing apparatus as claimed in claim 15 , wherein said total first bit-width is 21 bits and said third bit-width is 64 bits.

20. The data processing apparatus as claimed in claim 16 , wherein said calculation of said partial address result comprises expanding said first bit-width to said second bit-width corresponding to said frame offset value by multiplying said at least one frame offset field by said frame size and expanding said second bit-width to said third bit-width corresponding to said full address by performing a sign extension.

21. The data processing apparatus as claimed in claim 16 , wherein upon execution of said at least one supplementary program instruction, said frame offset value is added to said intra-frame offset value to generate a combined offset value corresponding to said full address and wherein said combined offset value specifies a location of said information entity relative to said non-fixed reference address.

22. The data processing app

Assignees

• Stephens Nigel John
• Seal David James
• Advanced Risc Mach Ltd

Inventors

• Stephens Nigel John
• Seal David James

Classifications

• G06F9/3557 Primary

  using program counter as base address · CPC title

• G06F9/342

  Extension of operand address space · CPC title

• G06F9/30007

  to perform operations on data operands · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/30167 Primary

  of immediate specifier, e.g. constants · CPC title