All-tungsten scheme for source/drain contact, source/drain via, and gate via
US-2024395618-A1 · Nov 28, 2024 · US
Method for manufacturing semiconductor device
US8951908B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8951908-B2 |
| Application number | US-201414221711-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 21, 2014 |
| Priority date | Sep 21, 2011 |
| Publication date | Feb 10, 2015 |
| Grant date | Feb 10, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A method for manufacturing semiconductor device includes preparing a structure including a substrate, an insulating layer on the substrate and having a recess, a barrier film on the insulating layer, and a copper film on the barrier such that the copper film is filling the recess with the barrier between the insulating layer and copper film, removing the copper film down to interface with the barrier such that copper wiring is formed in the recess, etching the wiring such that surface of the wiring is recessed from surface of the insulating layer, and removing the barrier from the surface of the insulating layer such that the surface of the insulating layer is exposed. The etching includes positioning the structure removed down to the barrier in organic compound atmosphere having vacuum state, and irradiating oxygen gas cluster ion beam on the surface of the wiring to anisotropically etch the wiring.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a semiconductor device, comprising: preparing a structure comprising a substrate, an interlayer insulating layer formed on the substrate and having a recessed portion, a barrier film formed on the interlayer insulating layer, and a copper film formed on the barrier film such that the copper film is filling the recessed portion of the interlayer insulating layer with the barrier film interposed between the interlayer insulating laye…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10W20/425Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8951908B2 cover?
- A method for manufacturing semiconductor device includes preparing a structure including a substrate, an insulating layer on the substrate and having a recess, a barrier film on the insulating layer, and a copper film on the barrier such that the copper film is filling the recess with the barrier between the insulating layer and copper film, removing the copper film down to interface with the b…
- Who is the assignee on this patent?
- Tokyo Electron Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W20/425. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).