Debonding temporarily bonded semiconductor wafers

US8950459B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8950459-B2
Application numberUS-201213662307-A
CountryUS
Kind codeB2
Filing dateOct 26, 2012
Priority dateApr 16, 2009
Publication dateFeb 10, 2015
Grant dateFeb 10, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Described methods and apparatus provide a controlled perturbation to an adhesive bond between a device wafer and a carrier wafer. The controlled perturbation, which can be mechanical, chemical, thermal, or radiative, facilitates the separation of the two wafers without damaging the device wafer. The controlled perturbation initiates a crack either within the adhesive joining the two wafers, at an interface within the adhesive layer (such as between a release layer and the adhesive), or at a wafer/adhesive interface. The crack can then be propagated using any of the foregoing methods, or combinations thereof, used to initiate the crack.

First claim

Opening claim text (preview).

What is claimed is: 1. A system for debonding a device wafer from a carrier wafer, the device wafer temporarily bonded to the carrier wafer, the system comprising: a wafer support structure configured for holding a wafer stack comprising the carrier wafer temporarily bonded to the device wafer by an adhesive layer; a crack initiator configured to initiate a crack in the adhesive layer by introducing a controlled perturbation with a tip of the crack initiator near an edge of the…

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What does patent US8950459B2 cover?
Described methods and apparatus provide a controlled perturbation to an adhesive bond between a device wafer and a carrier wafer. The controlled perturbation, which can be mechanical, chemical, thermal, or radiative, facilitates the separation of the two wafers without damaging the device wafer. The controlled perturbation initiates a crack either within the adhesive joining the two wafers, at …
Who is the assignee on this patent?
Suss Microtec Lithography Gmbh
What technology area does this patent fall under?
Primary CPC classification H10P72/74. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).