Layout design for electron-beam high volume manufacturing

Patent metadata

Field	Value
Publication number	US-8949749-B2
Application number	US-201213657992-A
Country	US
Kind code	B2
Filing date	Oct 23, 2012
Priority date	Oct 23, 2012
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines.

First claim

What is claimed is:

1. A method to create layout for electron-beam lithography, comprising:
assembling a layout comprising graphical data by arranging a plurality of standard cells within a design tool, a standard cell comprising one or more design shapes;
defining a layout grid for the layout within the design tool, wherein the layout grid comprises first vertical grid lines; and
reducing an amount of intersection between the design shapes and the first vertical grid lines by shifting one or more of the design shapes relative to the first vertical grid lines;
wherein reducing the amount of intersection between the design shapes and the first vertical grid lines comprises shifting the design shapes horizontally relative to the first vertical grid lines.

2. The method of claim 1 , wherein reducing the amount of intersection between the design shapes and the first vertical grid lines comprises avoiding first vertical grid lines with design shapes within the standard cell by shifting the standard cell horizontally, wherein design shapes comprise a width value below a first threshold or an area value below a second threshold.

3. The method of claim 1 , wherein reducing the amount of intersection between the design shapes and the first vertical grid lines comprises:
formulating a numerical description for a resulting number of interactions formed between design shapes and first vertical grid lines when exchanging positions between a plurality of standard cells of equal size for all possible exchange permutations; and
exchanging positions between the plurality of standard cells for an exchange permutation which minimizes the number of interactions.

4. The method of claim 1 , further comprising:
defining a vertical routing grid comprising second vertical grid lines, wherein periodicity of the layout grid is an integer multiple of periodicity of the vertical routing grid;
aligning the vertical routing grid to the layout grid resulting in coincidence between each first vertical grid line and a respective second vertical grid line; and
removing the respective second vertical grid line from the vertical routing grid.

5. The method of claim 1 , further comprising:
forming connections between two or more standard cells through placement of a plurality of shapes formed on a metallization layer;
constructing an vertical constraint graph for the plurality of shapes comprising one vertex for each shape and an edge formed between a first shape and a second shape which overlap in a horizontal direction;
weighting the edge by a value proportional to a distance between the first shape and the second shape; and
solving a minimization problem corresponding to the vertical constraint graph to determine placement of the plurality of shapes.

6. A method to create a layout for patterning by an electron beam (e-beam) writing tool, comprising:
assembling a layout by arranging a plurality of standard cells into rows using a design tool, wherein a standard cell comprises graphical data including one or more design shapes;
partitioning the layout into a plurality of subfields, wherein neighboring subfields abut one another at a stitching line;
defining a first violation density value as a number of via interconnect shapes within the standard cell straddling the stitching line;
defining a stitch-metal shape as an intersection of one of the plurality of subfields and a metallization layer straddling the stitching line;
defining a second violation density value within the standard cell as a number of subminimum sized stitch-metal shapes within the standard cell straddling the stitching line;
defining a third violation density value within the standard cell as a number of vertical metallization shapes bisected by the stitching line;
defining a violation density value for the standard cell as a sum of the first violation density value, the second violation density value, and the third violation density value; and
shifting at least one of the one or more design shapes from the stitching line to reduce a number of design shapes that straddle the stitching line.

7. The method of claim 6 , wherein the graphical data comprises a GL1, OASIS, or GDSII data format.

8. The method of claim 6 , further comprising moving the standard cell along a direction orthogonal to the stitching line to reduce the violation density value.

9. The method of claim 8 , further comprising:
determining the violation density value of each standard cell within a respective row of the layout;
moving a first standard cell comprising a largest violation density value within the row along the direction orthogonal to the stitching line to minimize the largest violation density value within the first standard cell; and
moving a second standard cell comprising a second largest violation density value within the row along the direction orthogonal to the stitching line to minimize the second largest violation density value within the second standard cell.

10. The method of claim 6 , further comprising:
defining a checking tile to cover portions of two or more rows of standard cells within the layout;
determining a total violation density value within the checking tile as a sum of violation density values within standard cells covered by the checking tile; and
minimizing the total violation density value by swapping a first standard cell within the checking tile with a second standard cell within the checking tile.

11. The method of claim 10 further comprising swapping three or more cells by:
constructing a bipartite graph between a first set of shapes comprising a plurality of standard cells of equal size within the checking tile and a second set of shapes comprising locations of the plurality of standard cells;
weighting an edge formed between a standard cell from the first set of shapes and a location from the second set of shapes by the total violation density value resulting from placing the standard cell at the location; and
solving a minimum weight maximum bipartite matching problem to minimize a sum of total violation density values along all edges of the bipartite graph to find an optimal swapping solution for placement of the standard cells from the first set of shapes in the locations from the second set of shapes.

12. The method of claim 11 , further comprising weighting an edge formed between the standard cell and a location by a sum of:
a product of a first weighting factor and a first violation density value resulting from placing the standard cell at the location;
a product of a second weighting factor and a second violation density value resulting from placing the standard cell at the location; and
a product of a third weighting factor and a number of design shapes that straddle the stitching line.

13. The method of claim 6 , further comprising:
partitioning a subfield into a plurality of tiles;
forming connections between two or more standard cells within the subfield through placement of a plurality of shapes formed on one of a plurality of metallization layers;
constructing a vertical constraint graph comprising one vertex for each shape and an edge formed between a first vertex corresponding to a first shape, and a second vertex corresponding to a second shape, wherein the first shape and the second shape overlap in a horizontal direction;
weighting the edge by a value of one-half raised to a value of a distance between the first shape and the second shape; and
solving a minimization problem corresponding to the vertical constraint graph to determine placement of the plurality of shapes.

14. The method of claim 13 , further comprising:
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Assignees

• Taiwan Semiconductor Mfg
• Taiwan Semiconductor Mfg

Inventors

• Wang Hung-Chun
• Fang Shao-Yun
• Lin Tzu-Chin
• Huang Wen-Chun
• Liu Ru-Gun

Classifications

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• Y02P90/02

  Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] · CPC title