Memory system and host device
US-2024394189-A1 · Nov 28, 2024 · US
US8949541B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949541-B2 |
| Application number | US-201113296119-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 14, 2011 |
| Priority date | Dec 8, 2008 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes may include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.
Opening claim text (preview).
We claim: 1. A method for cleaning dirty data resident in an intermediate cache that is coupled to one or more clients and to an external memory, the method comprising: examining one or more entries in a notification sorter that are each affirmatively associated with one bank page of the external memory, wherein said each affirmatively associated entry includes a first count indicating a first number of dirty data notifications, each of which is associated with a cache line in the…
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