Method and apparatus for verifying integrity in memory-disaggregated environment
US-12153525-B2 · Nov 26, 2024 · US
US8949530B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8949530-B2 |
| Application number | US-201113196071-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 2, 2011 |
| Priority date | Aug 2, 2011 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Systems and methods are disclosed for improving the performance of cache memory in a computer system by dynamically selecting an index for caching main memory while an application is running. A disclosed example of a memory system includes a cache including a data array, a primary tag array, and at least one secondary tag array. A currently selected index is used to index data bits to the data array and tag bits to the primary tag array. The performance of at least one candidate index is evaluated by indexing tag bits to the secondary tag array, without caching any data using the candidate index while the candidate index is under evaluation. If the candidate index has a better hit rate than the currently selected index, the memory system switches to using the candidate index to cache data.
Opening claim text (preview).
What is claimed is: 1. A method for improving performance of cache memory in a computer, comprising: the computer running a software application that generates memory blocks to be stored in memory; a cache controller indexing data bits of the memory blocks to a data array in the cache memory using a currently selected index; the cache controller simultaneously indexing tag bits of the memory blocks to a primary tag array using the currently selected index and indexing tag bits…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.