Semiconductor arrangement and method for producing a semiconductor arrangement

Patent metadata

Field	Value
Publication number	US-8946885-B2
Application number	US-200913063652-A
Country	US
Kind code	B2
Filing date	Jul 13, 2009
Priority date	Sep 12, 2008
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

A semiconductor arrangement includes a ceramic mount and at least one semiconductor component fixed-to the ceramic mount. The ceramic mount includes a first section, and the first section is electrically conductive.

First claim

The invention claimed is:

1. A semiconductor arrangement, comprising:
a ceramic mount; and
at least one semiconductor component fixed to a first side of the ceramic mount,
wherein the ceramic mount includes
at least one electrically conductive area formed of an electrically conductive ceramic material,
wherein the ceramic mount includes at least one electrically non-conductive area formed of an electrically non-conductive ceramic material, and
wherein the at least one electrically conductive area and the at least one electrically non-conductive area are arranged alongside one another in relation to the first side.

2. The semiconductor arrangement as claimed in claim 1 , wherein the at least one semiconductor component is composed of a semiconductor material that includes SiC.

3. The semiconductor arrangement as claimed in claim 1 , wherein the ceramic mount and the at least one semiconductor component have at least approximately the same coefficient of thermal expansion.

4. The semiconductor arrangement as claimed in claim 1 , wherein:
at least the first section of the ceramic mount and the at least one semiconductor component are formed from the same ceramic material.

5. The semiconductor arrangement as claimed in claim 1 , further comprising at least one interconnect connected between the at least one semiconductor component and the ceramic mount, wherein the electrically non-conductive area is arranged to support the at least one interconnect.

6. The semiconductor arrangement as claimed in claim 1 , wherein the electrically conductive area and the electrically non-conductive area are arranged alongside one another on a substantially two-dimensional plane or in a three-dimensional structure.

7. The semiconductor arrangement as claimed in claim 1 , wherein the semiconductor component is connected to the ceramic mount by silver sintering.

8. The semiconductor arrangement as claimed in claim 7 , wherein:
the semiconductor component is connected to the ceramic mount by silver sintering with the involvement of at least one metallic auxiliary layer, and
the auxiliary layer is applied to the at least one semiconductor component by rear-face coating.

9. The semiconductor arrangement as claimed in claim 7 , wherein the at least one semiconductor component is connected to the ceramic mount by silver sintering which forms a metallic auxiliary layer between the semiconductor component and the ceramic mount, the auxiliary layer being in the form of a thin film with a thickness of less than 5 μm.

10. The semiconductor arrangement as claimed in claim 1 , wherein:
the ceramic mount has a mechanical function structure section, and
the mechanical function structure section includes one of an attachment section, a heat-sink section, and a bearing section.

11. The semiconductor arrangement as claimed in claim 1 , wherein:
the ceramic mount has a mechanical function structure section, and
the mechanical function structure section comprises an opening for holding an attachment element, and/or an alignment tab, and/or a latching tab, and/or an attachment pin.

12. The semiconductor arrangement as claimed in claim 1 , wherein:
the at least one semiconductor component has a band gap, and
the band gap is greater than 2 eV.

13. The semiconductor arrangement as claimed in claim 1 , wherein the ceramic mount includes two electrically conductive areas formed of electrically conductive ceramic material, and
wherein the two electrically conductive areas and the at least one electrically non-conductive are arranged alongside each other in relation to the first side with the two electrically conductive areas being separated by the at least one electrically non-conductive area.

14. The semiconductor arrangement as claimed in claim 13 , wherein the semiconductor component is electrically connected to the two electrically conductive areas.

15. The semiconductor arrangement as claimed in claim 13 , wherein the two electrically conductive areas are isolated from each other by the at least one non-electrically conductive area.

Assignees

• Krauss Andreas
• Bosch Gmbh Robert

Inventors

• Krauss Andreas

Classifications

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W70/24

  characterised by materials · CPC title

• H10W70/692 Primary

  Ceramics or glasses · CPC title

• H01L23/15 Primary

  Electricity · mapped topic