FinFET device structure and methods of making same

US8946014B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8946014-B2
Application numberUS-201313748312-A
CountryUS
Kind codeB2
Filing dateJan 23, 2013
Priority dateDec 28, 2012
Publication dateFeb 3, 2015
Grant dateFeb 3, 2015

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Abstract

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Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a FinFET device, a FinFET device. An embodiment a method for semiconductor device, the method comprising forming a first dielectric layer over a substrate, forming a first hardmask layer over the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further comprises forming a first raised portion of the first dielectric layer with the first width, wherein the first raised portion is aligned with the first hardmask portion, and forming a first spacer and a second spacer over the first dielectric layer, wherein the first spacer and the second spacer are on opposite sides of the first raised portion, and wherein the sidewalls of the first spacer and the second spacer are substantially orthogonal to the top surface of the substrate.

First claim

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What is claimed is: 1. A method of forming a semiconductor device, the method comprising: forming a first dielectric layer over a substrate forming a first hardmask layer over the first dielectric layer; patterning the first hardmask layer to form a first hardmask portion with a first width; forming a first raised portion of the first dielectric layer with the first width, wherein the first raised portion is aligned with the first hardmask portion; forming a first spacer a…

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What does patent US8946014B2 cover?
Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a FinFET device, a FinFET device. An embodiment a method for semiconductor device, the method comprising forming a first dielectric layer over a substrate, forming a first hardmask layer over the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portio…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg
What technology area does this patent fall under?
Primary CPC classification H10D84/0158. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).