Oxide material and semiconductor device
US-2024395942-A1 · Nov 28, 2024 · US
Wafer warpage reduction
US8945971B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8945971-B2 |
| Application number | US-201313936254-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 8, 2013 |
| Priority date | Mar 12, 2013 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
Official abstract text for this publication.
The present disclosure relates a method to mitigate wafer warpage in advanced technology manufacturing processes due to crystallization of one or more amorphous layers with asymmetrical front-surface and back-surface layer thicknesses. After deposition of one or more layers of amorphous material on a front-surface and a back-surface of the wafer in a furnace tool, the front-surface layers are patterned which thins a front layer thickness. Downstream thermal processing performed at a temperature which exceeds a crystallization threshold of the amorphous material will result in asymmetric stress between the front and back surfaces due to the asymmetrical layer thicknesses. To mitigate this effect, the amount of warpage as a function of the difference in asymmetrical layer thickness may be determined such that a front-surface deposition tool may be utilized in conjunction with the furnace tool to reduce the difference in front-surface and back-surface layer thicknesses. Other methods are also disclosed.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of layer deposition on a substrate, comprising: depositing one or more first layers of amorphous material comprising a total first layer thickness on a front-surface and a back-surface of the substrate; depositing one or more second layers of the amorphous material comprising a total second layer thickness over the first layer on the front-surface; patterning the front-surface which thins a total thickness of the one or more first and second lay…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8945971B2 cover?
- The present disclosure relates a method to mitigate wafer warpage in advanced technology manufacturing processes due to crystallization of one or more amorphous layers with asymmetrical front-surface and back-surface layer thicknesses. After deposition of one or more layers of amorphous material on a front-surface and a back-surface of the wafer in a furnace tool, the front-surface layers are p…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10D62/40. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).