Laser scribing trench opening control in wafer dicing using hybrid laser scribing and plasma etch approach
US-2024079273-A1 · Mar 7, 2024 · US
High productivity combinatorial workflow for post gate etch clean development
US8945952B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8945952-B2 |
| Application number | US-201314071894-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 5, 2013 |
| Priority date | Jul 31, 2012 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.
First claim
Opening claim text (preview).
What is claimed is: 1. A method, comprising: forming a dielectric layer on a substrate; forming a plurality of metal gate stacks over the dielectric layer; defining site isolated regions on the substrate, wherein each site isolated region comprises at least one of the metal gate stacks; applying liquid chemicals to each of the site isolated regions, wherein at least one of the composition or the application condition of the liquid chemicals is varied in a combinatorial manne…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P70/273Primary
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8945952B2 cover?
- Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemic…
- Who is the assignee on this patent?
- Intermolecular Inc, Intermolecular Inc
- What technology area does this patent fall under?
- Primary CPC classification H10P70/273. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).