Random access memory and corresponding method for managing a random access memory
US-2024404613-A1 · Dec 5, 2024 · US
Combo static flop with full test
US8943375B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8943375-B2 |
| Application number | US-201213569833-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 8, 2012 |
| Priority date | Aug 8, 2012 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
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A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from the master latch circuit and a slave driver driven from the slave latch circuit.
First claim
Opening claim text (preview).
What is claimed is: 1. A SRAM (Static Random Access Memory) macro test flop circuit, driven by a source clock signal, comprising: a flip-flop circuit comprising: a master latch circuit comprising: a master storage node, and a three to one multiplexer with a first data-in, a second data-in, and a third data-in as three multiplexer inputs, wherein the multiplexer output provides a control signal for writing to the master storage node, and a slave latch circuit comprising: a…
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- G11C29/32Primary
Physics · mapped topic
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- What does patent US8943375B2 cover?
- A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan contr…
- Who is the assignee on this patent?
- Masleid Robert P, Vahidsafa Ali, Oracle Int Corp
- What technology area does this patent fall under?
- Primary CPC classification G11C29/32. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).