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Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
US8941235B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8941235-B2 |
| Application number | US-201213423262-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 18, 2012 |
| Priority date | Feb 27, 2001 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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- Title
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Abstract
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A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second die is less than or equal to a height of the bumps. A second substrate has a thermal conduction channel. A surface of the second semiconductor die opposite the first die is mounted to the thermal conductive channel of the second substrate. A thermal interface layer is formed over the surface of the second die. The bumps are electrically connected to contact pads on the second substrate. A conductive plane is formed over a surface of the second substrate.
First claim
Opening claim text (preview).
What is claimed: 1. A semiconductor device, comprising: a first substrate; a first semiconductor die mounted to the first substrate; a second semiconductor die mounted over the first semiconductor die, the second semiconductor die including an active surface oriented toward the first substrate; a second substrate including a thermal conduction channel, the second substrate being disposed over the first substrate with the second semiconductor die in thermal connection to the…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8941235B2 cover?
- A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second …
- Who is the assignee on this patent?
- Pendse Rajendra D, Stats Chippac Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W74/012. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).