Helical spiral inductor between stacking die

Patent metadata

Field	Value
Publication number	US-8941212-B2
Application number	US-201313760551-A
Country	US
Kind code	B2
Filing date	Feb 6, 2013
Priority date	Feb 6, 2013
Publication date	Jan 27, 2015
Grant date	Jan 27, 2015

Abstract

The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.

First claim

What is claimed is:

1. A multi-level integrated inductor, comprising:
a first inductive structure comprising a first conductive layer disposed onto a first integrated chip (IC) die;
a second inductive structure comprising a second conductive layer onto a second IC die vertically stacked onto the first IC die; and
a conductive interconnect structure located vertically between the first IC die and the second IC die and configured to electrically connect the first conductive laye…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yen Hsiao-Tsung
• Luo Cheng-Wei
• Kuo Chin-Wei
• Jeng Min-Chie

Classifications

• H10W90/734

  Electricity · mapped topic

• H10W90/732

  Electricity · mapped topic

• H10W90/724

  Electricity · mapped topic

• H10W90/722

  Electricity · mapped topic

• H10W74/15

  Electricity · mapped topic