Laminated wiring board and manufacturing method for same

US8941016B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8941016-B2
Application numberUS-201313734474-A
CountryUS
Kind codeB2
Filing dateJan 4, 2013
Priority dateJul 6, 2010
Publication dateJan 27, 2015
Grant dateJan 27, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A laminated wiring board, includes: a first substrate in which a conductor circuit is formed on one surface of an insulating layer and an adhesive layer is formed on an other surface of the insulating layer, and conductors are formed in via holes that pass through the insulating layer and the adhesive layer so that the conductor circuit is partially exposed therefrom; an electronic component electrically connected to the conductor circuit by allowing electrodes of the electronic component to be connected to the conductors; an embedding member arranged around the electronic components so that the electronic component is embedded therein; and a second substrate having an adhesive layer laminated to face the adhesive layer of the first substrate and sandwich the electronic component and the embedding member, wherein each of the electrodes of the electronic component is continuous with the conductor circuit through two or more of the conductors.

First claim

Opening claim text (preview).

What is claimed is: 1. A laminated wiring board, comprising: a first substrate in which a conductor circuit is formed on one surface of an insulating layer and an adhesive layer is formed on an other surface of the insulating layer, and conductors are respectively formed in a plurality of via holes that pass through the insulating layer and the adhesive layer so that the conductor circuit is partially exposed therefrom; an electronic component electrically connected to the condu…

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What does patent US8941016B2 cover?
A laminated wiring board, includes: a first substrate in which a conductor circuit is formed on one surface of an insulating layer and an adhesive layer is formed on an other surface of the insulating layer, and conductors are formed in via holes that pass through the insulating layer and the adhesive layer so that the conductor circuit is partially exposed therefrom; an electronic component el…
Who is the assignee on this patent?
Fujikura Ltd
What technology area does this patent fall under?
Primary CPC classification H05K1/183. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).