Electronic component package and method for manufacturing electronic component package
US-2024090133-A1 · Mar 14, 2024 · US
Mechanism for MEMS bump side wall angle improvement
US8940586B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8940586-B2 |
| Application number | US-201113303754-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 23, 2011 |
| Priority date | Nov 23, 2011 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
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The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of bump processing, comprising: forming a first masking layer on a substrate comprising a dielectric layer having one or more metal interconnect layers to define a first etching area; forming one or more anti-stiction bumps by etching the substrate in the first etching area; forming a second masking layer, which exposes the one or more anti-stiction bumps, to define a second etching area that contains the one or more anti-stiction bumps; and f…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W76/15Primary
Electricity · mapped topic
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- What does patent US8940586B2 cover?
- The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of t…
- Who is the assignee on this patent?
- Kuo Chris, Tseng Lee-Chuan, Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W76/15. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).