Dual-gate bio/chem sensor

Patent metadata

Field	Value
Publication number	US-8940569-B2
Application number	US-201213651867-A
Country	US
Kind code	B2
Filing date	Oct 15, 2012
Priority date	Oct 15, 2012
Publication date	Jan 27, 2015
Grant date	Jan 27, 2015

Abstract

A dual gate extremely thin semiconductor-on-insulator transistor with asymmetric gate dielectrics is provided. This structure can improve the sensor detection limit and also relieve the drift effects. Detection is performed at a constant current mode while the species will be detected at a gate electrode with a thin equivalent oxide thickness (EOT) and the gate bias will be applied to the second gate electrode with thicker EOT to maintain current flow through the transistor. As a result, a small change in the charge on the first electrode with the thin EOT will be translated into a larger voltage on the gate electrode with the thick EOT to sustain the current flow through the transistor. This allows a reduction of the sensor dimension and therefore an increase in the array size. The dual gate structure further includes cavities, i.e., microwell arrays, for chemical sensing.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming non-contiguous first conductivity type semiconductor regions within a semiconductor base layer of a semiconductor-on-insulator substrate, said semiconductor-on-insulator substrate further comprise at least one buried dielectric material layer having a first thickness located on a surface of the semiconductor base layer, and a semiconductor-on-insulator layer located on an uppermost surface of said at least one buried dielectric material layer;
patterning said semiconductor-on-insulator layer forming an active device region;
forming a transistor within said active device region, wherein said transistor comprises a gate dielectric material having a second thickness, wherein said second thickness of said gate dielectric material is less than said first thickness of said at least one buried dielectric material layer;
forming an interconnect structure straddling said transistor located within said active device region;
removing a portion of said semiconductor base layer of said semiconductor-on-insulator substrate stopping on a surface of each of said non-contiguous first conductivity type semiconductor regions and providing a cavity between the non-contiguous first conductivity type semiconductor regions that exposes a portion of the at least one buried dielectric material layer; and
thinning the exposed portion of the at least one buried dielectric material layer to a third thickness which is less than the second thickness of the at least one gate dielectric material layer of the transistor.

2. The method of claim 1 , wherein each of said non-contiguous first conductivity type semiconductor regions has a surface in direct contact with a surface of the at least one buried dielectric material layer.

3. The method of claim 1 , wherein each of said non-contiguous first conductivity type semiconductor regions has a surface in direct contact with a portion of the semiconductor base layer.

4. The method of claim 1 , wherein said forming said non-contiguous first conductivity type semiconductor regions comprises forming a patterned implantation mask on a surface of said semiconductor-on-insulator layer, wherein said patterned implantation mask protects at least one portion of said semiconductor-on-insulator layer, while leaving other portions of said semiconductor-on-insulator layer exposed, and implanting a first conductivity type dopant through said exposed portions of said semiconductor-on-insulator layer.

5. The method of claim 1 , wherein said removing said portion of said semiconductor base layer comprises a controlled spalling process.

6. The method of claim 5 , wherein said controlled spalling process comprises forming at least a stressor layer on an exposed surface of the interconnect structure.

7. The method of claim 6 , wherein said stressor layer comprises a metal.

8. The method of claim 6 , wherein said controlled spalling is performed at room temperature or at a temperature below room temperature.

9. The method of claim 5 , wherein after said controlled spalling process an isotropic etching process is employed to remove further portions of said semiconductor base layer.

10. The method of claim 1 , wherein said thinning said exposed portion of the at least buried dielectric material layer comprises a wet chemical etching process.

11. The method of claim 1 , wherein said removing said portion of said semiconductor base layer comprises a planarization process, followed by an isotropic etching process.

12. The method of claim 1 , wherein said removing said portion of said semiconductor base layer comprises isotropic etching.

13. The method of claim 1 , wherein another active device region is formed during said patterning said semiconductor-on-insulator layer, and wherein a pair of transistors are formed within said another active device region during said forming said transistor, and further wherein during said forming said interconnect structure a metal contact is formed that connects one of the pair of said transistors in said another device region to said transistor in said device region.

14. The method of claim 1 , wherein after thinning the exposed portion of the at least one buried dielectric material layer a another cavity is formed between the non-contiguous first conductivity type semiconductor regions, and wherein a passivation layer is formed on exposed surfaces of the non-contiguous first conductivity type semiconductor regions and within said another cavity.

Assignees

• IBM

Inventors

• Bedell Stephen W
• Hekmatshoartabari Bahman
• Shahidi Ghavam G
• Shahrjerdi Davood

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10D86/01 Primary

  Manufacture or treatment · CPC title

• H10D30/6734 Primary

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10P30/212

  Through-implantation · CPC title