Semiconductor device including buried contact and method for manufacturing the same
US-12178034-B2 · Dec 24, 2024 · US
Method of semiconductor integrated circuit fabrication
US8937006B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8937006-B2 |
| Application number | US-201213561263-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 30, 2012 |
| Priority date | Jul 30, 2012 |
| Publication date | Jan 20, 2015 |
| Grant date | Jan 20, 2015 |
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Abstract
Official abstract text for this publication.
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device. The method also includes forming a step-forming-hard-mask (SFHM) on the MG stack in a predetermined area on the semiconductor substrate, performing MG recessing, depositing a MG hard mask over the semiconductor substrate and recessing the MG hard mask to fully remove the MG hard mask from the MG stack in the predetermined area.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising: receiving a semiconductor device, the semiconductor device including: a semiconductor substrate; a metal gate (MG) stack on the semiconductor substrate; a source and a drain separated by the metal gate stack on the semiconductor substrate; and a first interlayer dielectric (ILD) layer on the semiconductor substrate; forming a step-forming-hard-mask (SFHM) on t…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10W20/069Primary
Electricity · mapped topic
Electricity · mapped topic
- H10D84/0135Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8937006B2 cover?
- A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device. The method also includes forming a step-forming-hard-mask (SFHM) on the MG stack in a predetermined area on the semiconductor substrate, performing MG recessing, depositing a MG hard mask over the semiconductor substrate and recessing the MG hard mask to fully remo…
- Who is the assignee on this patent?
- Liang Minchang, Lin Chie-Iuan, Wu Yao-Kwang, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/069. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 20 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).