Hybrid substrate with improved isolation and simplified method for producing a hybrid substrate

US8936993B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8936993-B2
Application numberUS-97625010-A
CountryUS
Kind codeB2
Filing dateDec 22, 2010
Priority dateDec 22, 2009
Publication dateJan 20, 2015
Grant dateJan 20, 2015

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Abstract

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A hybrid substrate comprises first and second active areas made from semiconductor materials laterally offset from one another and separated by an isolation area. The main surfaces of the isolation area and of the first active area form a plane. The hybrid substrate is obtained from a source substrate successively comprising layers made from a first and second semiconductor materials separated by an isolation layer. A single etching mask is used to pattern the isolation area, first active area and second active area. The main surface of the first active area is released thereby forming voids in the source substrate. The etching mask is eliminated above the first active area. A first isolation material is deposited, planarized and etched until the main surface of the first active area is released.

First claim

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The invention claimed is: 1. A method for producing a hybrid substrate comprising successively: providing a substrate successively comprising a layer made from a first semiconductor material, an isolation layer, a layer made from a second semiconductor material, and an etching mask including first and second covering areas separated by an uncovered area, etching the layer made from the second semiconductor material, the isolation layer, and the layer made from the first semicond…

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What does patent US8936993B2 cover?
A hybrid substrate comprises first and second active areas made from semiconductor materials laterally offset from one another and separated by an isolation area. The main surfaces of the isolation area and of the first active area form a plane. The hybrid substrate is obtained from a source substrate successively comprising layers made from a first and second semiconductor materials separated …
Who is the assignee on this patent?
Fenouillet-Béranger Claire, Denorme Stéphane, Coronel Philippe, and 2 more
What technology area does this patent fall under?
Primary CPC classification H10P90/1906. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 20 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).