Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Patent metadata

Field	Value
Publication number	US-8936977-B2
Application number	US-201213482393-A
Country	US
Kind code	B2
Filing date	May 29, 2012
Priority date	May 29, 2012
Publication date	Jan 20, 2015
Grant date	Jan 20, 2015

Abstract

A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.

First claim

What is claimed is:

1. A method comprising:
forming first and second high-k metal gate (HKMG) gate stacks on a substrate;
forming a nitride liner and oxide spacers on each side of each of the first and second HKMG gate stacks, such that the nitride liner is in direct contact with the first and second HKMG gate stacks;
performing halo/extension implants at each side of each of the first and second HKMG gate stacks;
forming an oxide liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks;
forming deep source/drain regions at opposite sides of the second HKMG gate stack;
forming an oxide hardmask over the second HKMG gate stack;
forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack; and
removing the oxide hardmask.

2. The method according to claim 1 , comprising:
forming the nitride liner of silicon nitride (SiN);
forming the oxide spacers of SiO2; and
forming the nitride spacers of SiN.

3. The method according to claim 1 , wherein the first and second HKMG gate stacks each further comprises a high-k dielectric, a work function metal, polysilicon (poly-Si), and a SiN cap.

4. The method according to claim 3 , further comprising:
precleaning prior to forming the eSiGe; and
optimizing the precleaning to protect the SiO2 spacers.

5. The method according to claim 1 , comprising:
forming eSiGe at each side of the first HKMG gate stack by:
forming a cavity by wet etching with tetramethylammonium hydroxide (TMAH); and
epitaxially growing SiGe in the cavity.

6. The method according to claim 5 , further comprising implanting a boron dopant in-situ into the eSiGe.

7. The method according to claim 6 , comprising implanting boron with a graded doping profile.

8. The method according to claim 1 , further comprising annealing to activate implanted dopants after forming the oxide hardmask.

9. The method according to claim 1 , comprising removing oxide hardmask by wet etching with diluted hydrofluoric acid (dHF).

10. The method according to claim 9 , further comprising removing the SiN cap and nitride spacers after removing the oxide hardmask.

11. The method according to claim 10 , comprising removing the SiN cap and nitride spacer by a dry or wet etch process.

12. The method according to claim 11 , further comprising forming a silicide on the source/drain regions, the eSiGe, and the first and second HKMG gate stacks.

13. The method according to claim 1 , further comprising forming a channel SiGe region below the first HKMG gate stack.

14. A method comprising:
forming PMOS and NMOS high-k metal gate (HKMG) gate stacks on a substrate;
forming an L-shaped silicon nitride (SiN) liner and silicon dioxide (SiO2) spacers on each side of each of the PMOS and NMOS HKMG gate stacks, such that the SiN liner is in direct contact with the PMOS and NMOS HKMG gate stacks;
performing halo/extension implants at each side of each of the PMOS and NMOS HKMG gate stacks;
forming an L-shaped SiO2 liner and SiN spacers on the SiO2 spacers of each of the PMOS and NMOS HKMG gate stacks;
implanting deep source/drain regions at opposite sides of the NMOS HKMG gate stack;
forming an SiO2 hardmask over the NMOS HKMG gate stack;
forming embedded silicon germanium (eSiGe) at opposite sides of the PMOS HKMG gate stack by:
forming a cavity at each side of the PMOS HKMG gate stack by wet etching with TMAH;
epitaxially growing SiGe in the cavity; and
implanting a boron dopant, with a graded doping profile, in-situ into the eSiGe concurrently with the epitaxial growth;
wet etching the SiO2 hardmask with diluted hydrofluoric acid (dHF);
dry or wet etching the SiN cap and SiN spacers; and
forming a silicide on the source/drain regions, the eSiGe, and the PMOS and NMOS HKMG gate stacks.

Assignees

• Hoentschel Jan
• Ong Shiang Yang
• Flachowsky Stefan
• Scheiper Thilo
• Globalfoundries Sg Pte Ltd

Inventors

• Hoentschel Jan
• Ong Shiang Yang
• Flachowsky Stefan
• Scheiper Thilo

Classifications

• H10P30/225

  of a molecular ion, e.g. decaborane · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0167 Primary

  Manufacturing their channels · CPC title