Data Encoding in Solid-State Storage Devices
US-2015380087-A1 · Dec 31, 2015 · US
Method for reducing effective raw bit error rate in multi-level cell NAND flash memory
US8935599B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935599-B2 |
| Application number | US-201414180286-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 13, 2014 |
| Priority date | Mar 15, 2013 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory system comprising: a flash subsystem grouped into pages of data, the pages of data including error correcting code (ECC) and being identified by page numbers, at least some of the pages of data having a lower page of data and an upper page of data, wherein the lower and upper pages of data form a pair; a flash controller coupled to the flash subsystem, the flash controller configured to split the ECC; and a buffer including a page of data from t…
Assignees
Inventors
Classifications
Physics · mapped topic
Physics · mapped topic
- G06F11/1072Primary
Physics · mapped topic
- G06F11/1068Primary
Physics · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8935599B2 cover?
- A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein spli…
- Who is the assignee on this patent?
- Avalanche Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F11/1072. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).