Power supply monitor for detecting faults during scan testing
US-9194914-B2 · Nov 24, 2015 · US
Removing scan channel limitation on semiconductor devices
US8935583B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935583-B2 |
| Application number | US-201213477150-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 22, 2012 |
| Priority date | May 22, 2012 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit is coupled to a logic block to be scan tested. The output from the logic block is coupled to a serial output pin on the integrated circuit during scan test mode. High performance integrated circuits can use SerDes pins in a scan test mode to be scan tested without impacting mission critical signals.
First claim
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What is claimed is: 1. A method to perform component testing, the method comprising: supplying a test pattern to a serial input pin on an integrated circuit, the serial input pin being coupled to a boundary-scan cell that is associated with a test receiver; configuring the test receiver to operate in a scan test mode; coupling output of the test receiver during the scan test mode to a logic block to be scan tested; and coupling output from the logic block to a serial output…
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Physics · mapped topic
- G01R31/318547Primary
Physics · mapped topic
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- What does patent US8935583B2 cover?
- A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit is coupled to a logic block to be scan tested. The output from the logic block is coupled to a serial out…
- Who is the assignee on this patent?
- Jun Hongshin, Eklow William, Kim Sun-Gyu, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G01R31/318547. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).