Semiconductor test system and method
US-9222977-B2 · Dec 29, 2015 · US
US8935582B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935582-B2 |
| Application number | US-201213460407-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 30, 2012 |
| Priority date | Mar 4, 2007 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Official abstract text for this publication.
Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.
Opening claim text (preview).
What is claimed is: 1. One or more computer-readable storage media storing computer-executable instructions for causing a computer to perform a method, the method comprising: performing a first test pattern generation technique targeting a fault caused by a possible defect at a scan cell N of a scan chain, the first test pattern generation technique being designed to generate a single test pattern for detecting the fault at the scan cell N; and performing a second test pattern g…
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