Memory disaggregation in a multi-node environment
US-2024020174-A1 · Jan 18, 2024 · US
Memory access for digital signal processing
US8935486B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935486-B2 |
| Application number | US-201213563204-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 31, 2012 |
| Priority date | Nov 9, 2011 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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Memory access in a digital signal processing system is described. In one example, the digital signal processing system comprises a multi-port memory that is constructed from a memory interface connected to a number of single-port memory devices. The memory interface provides access ports that processors can use to access data stored on the single-port memory devices using a single address space. A processor can be connected to several access ports, and use these to request access to data at several different memory addresses at the same time. The digital signal processing system is configured such that the total number of single-port memory devices connected to the memory interface is a prime number greater than or equal to three. Because a prime number of memory devices are used, the likelihood of the data for the different memory addresses being on the same single-port memory device is minimised, increasing memory access speed.
First claim
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The invention claimed is: 1. A digital signal processing system, comprising: a plurality of single-port memory devices; a memory interface connected to the plurality of single-port memory devices and comprising a plurality of access ports, wherein the memory interface is arranged to provide access to the plurality of single-port memory devices through each access port using a single address space; and a processor having a plurality of data connections that couple the processor t…
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- G06F13/1657Primary
Physics · mapped topic
- G06F13/1663Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US8935486B2 cover?
- Memory access in a digital signal processing system is described. In one example, the digital signal processing system comprises a multi-port memory that is constructed from a memory interface connected to a number of single-port memory devices. The memory interface provides access ports that processors can use to access data stored on the single-port memory devices using a single address space…
- Who is the assignee on this patent?
- Anderson Adrian John, Wass Gary Christopher, Imagination Tech Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F13/1657. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).