Complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier

Patent metadata

Field	Value
Publication number	US-8934286-B2
Application number	US-201313747529-A
Country	US
Kind code	B2
Filing date	Jan 23, 2013
Priority date	Jan 23, 2013
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

A complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier is described. In one embodiment, the DRAM cell includes an n-type field-effect transistor (NFET), a p-type field-effect transistor (PFET), and a storage capacitor accessed through both the NFET and the PFET. A pair of bit lines is coupled to the DRAM cell. A sense amplifier with a single-ended read path reads data in the DRAM cell through only one of the bit lines and a data-dependent write-back path writes back data to the DRAM cell through either one of the bit lines. The bit line used by the sense amplifier to write back the data to the DRAM cell depends on the logical value of the data.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) cell, comprising:
a pair of bit lines;
a storage capacitor;
an n-type field-effect transistor (NFET) access transistor selected by a first word line that couples the storage capacitor to one of the pair of bit lines; and
a p-type field-effect transistor (PFET) access transistor selected by a second word line that couples the storage capacitor to another of the pair of bit lines;
wherein only one bit line from the…

Assignees

• IBM

Inventors

• Barth Jr John E
• Vehabovic Adis

Classifications

• G11C11/403

  Physics · mapped topic

• G11C8/16 Primary

  Physics · mapped topic

• G11C11/4096

  Physics · mapped topic

• G11C11/4094

  Physics · mapped topic