Method and system for fast synchronized dynamic switching of a reconfigurable phase locked loop (PLL) for near field communications (NFC) peer to peer (P2P) active communications

Patent metadata

Field	Value
Publication number	US-8933733-B2
Application number	US-201314072719-A
Country	US
Kind code	B2
Filing date	Nov 5, 2013
Priority date	Jan 7, 2013
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

A reconfigurable circuit is disclosed. The reconfigurable circuit comprises a pause detector mechanism, a clock extractor, and a multiplexer. The multiplexer is configured to receive a reference clock and is coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field. The reconfigurable circuit also comprises a phase locked loop (PLL) coupled to the pause detector mechanism and the multiplexer, and the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be locked to the extracted clock, and in a third mode wherein the PLL can switch between being locked to the reference clock and being locked to the extracted clock.

First claim

What is claimed is:

1. A reconfigurable circuit comprising:
a pause detector mechanism;
a clock extractor;
a multiplexer configured to receive a reference clock and coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field; and
a phase locked loop (PLL) coupled to pause detector mechanism and the multiplexer, wherein the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be…

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Choke Tieng Ying
• Sun Yuan
• Zhang Huajiang
• Shana A Osama K A

Classifications

• H04B5/0056

  Electricity · mapped topic

• H03L7/083 Primary

  Electricity · mapped topic

• H03L7/0898

  Electricity · mapped topic

• H03L7/0807

  Electricity · mapped topic

• H03L7/093

  Electricity · mapped topic