Method of forming a gate structure
US-2024332089-A1 · Oct 3, 2024 · US
Advanced forming method and structure of local mechanical strained transistor
US8933503B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933503-B2 |
| Application number | US-201113077641-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 31, 2011 |
| Priority date | Jun 9, 2006 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A strained channel transistor, comprising: a gate electrode over a semiconductor crystal substrate, wherein an interatomic distance between neighboring atoms in the semiconductor crystal is defined by a substrate lattice spacing; sidewall spacers on the gate electrode; source and drain regions formed entirely within the semiconductor crystal substrate on opposite sides of the gate electrode, the source and drain regions each having a planar uppermost sur…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8933503B2 cover?
- Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may …
- Who is the assignee on this patent?
- Chen Chien-Hao, Lee Tze-Liang, Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10D30/792. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).