Method of sharing and re-using timing models in a chip across multiple voltage domains

Patent metadata

Field	Value
Publication number	US-8930864-B2
Application number	US-201213633911-A
Country	US
Kind code	B2
Filing date	Oct 3, 2012
Priority date	Oct 3, 2012
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts.

First claim

What is claimed is:

1. A method for sharing and re-using a single voltage parameterized statistical timing model corresponding to a macro during timing analysis of an integrated circuit (IC) chip design provided with at least one voltage domain and at least one instance of the macro, the method comprising:
a) using a computer, computing timings of said macro employing said macro single voltage parameterized statistical timing model;
b) obtaining information of voltage domain for macro instantiation;
c) comparing said voltage domain information of said macro instantiation with a voltage domain information of said single voltage parameterized statistical timing model to detect a voltage domain information mismatch;
d) generating a self-correction transformation upon discovery of said voltage domain information mismatch that dynamically updates said single voltage parameterized statistical timing model to correspond to said voltage domain of said macro instantiation;
e) dynamically updating results of said macro's said computed timings based on said dynamically updated statistical timing model; and
f) using said updated timing results, performing said timing analysis of said IC chip design.

2. The method of claim 1 , wherein in step f), said performing said timing analysis is a statistical timing analysis.

3. The method of claim 1 , wherein in step f), said performing said timing analysis is a deterministic corner based timing analysis.

4. The method of claim 1 , wherein said macro is instantiated at least once in said IC chip design at said one voltage domain corresponding to a fixed voltage.

5. The method of claim 1 , wherein said macro is instantiated at least once in said IC chip design at said one voltage domain corresponding to a voltage range that differs from that of said single voltage parameterized statistical timing model.

6. The method of claim 1 , wherein said macro is instantiated at least once in said IC chip design at said one voltage domain that is correlated with the voltage domain definition of said single voltage parameterized statistical timing model.

7. The method of claim 1 , wherein said macro is instantiated at least once in said chip design at said one voltage domain that varies independently from the voltage domain definition of said single voltage parameterized statistical timing model.

8. The method of claim 1 , wherein said statistical timing model comprises additional parameter sensitivities that are voltage dependent.

9. The method of claim 8 , wherein said dynamically updating the results of said timing analysis of said macro based on voltage domain conditions of said timing model updates additional parameter sensitivities that are voltage dependent.

10. The method of claim 1 further comprising performing in step a) timing calculations for said macro executed for a timing point at a time.

11. The method of claim 1 , further comprising performing in step a) timing calculations for said macro performed for a timing arc at a time.

12. The method of claim 1 , wherein results of said timing calculations comprise timing quantities consisting of delays, slews, waveforms, test guard-times, timing assertions, and sensitivities.

13. The method of claim 1 , wherein non-linear voltage mapping is performed for said dynamically updating the results of said timing calculations of said macro based on voltage domain conditions of said timing model.

14. The method of claim 1 , wherein statistical abstraction of said IC design is performed following said timing analysis of said IC design to generate a statistical timing abstract.

15. The method of claim 14 , wherein said IC design comprises only one of said macros to generate said statistical timing abstract of said macro at a new voltage domain condition.

16. The method of claim 14 , wherein said statistical timing abstract model further comprises bilinear non-separable canonical forms for characterized timing quantities.

17. The method of claim 16 , wherein during an instantiation of said generated statistical timing abstract, depending on a connected voltage domain, intrinsic value and parameter sensitivities of timing quantities are dynamically updated to reflect correct values corresponding to said domain.

18. The method of claim 1 further comprising ensuring timing of a hierarchical design with IP blocks at different domains are performed accurately without using pessimistic guard-bands, while keeping only a single statistical timing model or abstract for the IP.

19. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to, perform method steps for sharing and re-using a single voltage parameterized statistical timing model corresponding to a macro during timing analysis of an integrated circuit (IC) chip design provided with at least one voltage domain and at least one instance of the macro, the method comprising:
a) using a computer, computing timings of said macro employing said macro's single voltage parameterized statistical timing model;
b) obtaining information of voltage domain for macro instantiation;
c) comparing said voltage domain information of said macro instantiation with a voltage domain information of said single voltage parameterized statistical timing model, to detect a voltage domain information mismatch;
d) generating a self-correction transformation upon discovery of said voltage domain information mismatch that dynamically updates said single voltage parameterized statistical timing model to correspond to said voltage domain of said macro instantiation; and
e) dynamically updating results of said macro's said computed timings based on said dynamically updated statistical timing model; and
f) using said updated timing results, performing said timing analysis of said IC chip design.

Assignees

• IBM

Inventors

• Sinha Debjit
• Fluhr Eric J
• Shuma Stephen G
• Venkateswaran Natesan
• Visweswariah Chandramouli
• Wood Michael H
• Zolotov Vladimir

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title