Scan/scan enable D flip-flop

Patent metadata

Field	Value
Publication number	US-8928378-B2
Application number	US-77115710-A
Country	US
Kind code	B2
Filing date	Apr 30, 2010
Priority date	Mar 24, 2010
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

In accordance with an embodiment, an integrated circuit comprises a master-slave flip-flop, a selection logic circuit, and a pass structure. The selection logic circuit is configured to selectively enable or disable one or more clock signals. The pass structure is configured to pass a data signal to the master-slave flip-flop in response to a selected clock signal being enabled.

First claim

What is claimed is:

1. An integrated circuit comprising:
a master-slave flip-flop;
a selection logic circuit comprising first combinational logic circuitry and second combinational logic circuitry, the first combinational logic circuitry configured to selectively enable one or more of at least three clock signals in response to a control signal determined by the second combinational logic circuitry and selectively disable two or more of the at least three clock signals that were…

Assignees

• Wu Miaosong
• Taiwan Semiconductor Mfg

Inventors

• Wu Miaosong

Classifications

• H03K3/0372

  Electricity · mapped topic

• H03K3/0375 Primary

  Electricity · mapped topic

• G01R31/318541

  Physics · mapped topic