Hardware countermeasures in a fault tolerant security architecture
US-2024370591-A1 · Nov 7, 2024 · US
US8928372B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928372-B2 |
| Application number | US-201313791155-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 8, 2013 |
| Priority date | Mar 8, 2013 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.
Opening claim text (preview).
What is claimed is: 1. An electronic device comprising: a first circuit; a power on control (POC) circuit comprising: an enable terminal electrically connected to a first output of the first circuit; a first input terminal electrically connected to a first voltage supply; a second input terminal electrically connected to a second voltage supply; and an output terminal; and a second circuit comprising: a biasing-sensitive circuit; and a logic circuit comprising: a…
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