Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
Strained asymmetric source/drain
US8928094B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928094-B2 |
| Application number | US-87583410-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 3, 2010 |
| Priority date | Sep 3, 2010 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a silicon substrate; a metal gate formed on a top surface of the substrate; an offset spacer adjacent and physically contacting the gate on the substrate; a dopant implanted in the substrate to form a dopant region having a first type of dopant, wherein the dopant region extends under a portion of the offset spacer on a first side of the gate and does not extend under the offset spacer on a second, opposite side of th…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8928094B2 cover?
- The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendic…
- Who is the assignee on this patent?
- Cheng Chun-Fai, Fung Ka-Hing, Wang Shyh-Wei, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10D64/017. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).