Field-effect-transistor with self-aligned diffusion contact

US8928091B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8928091-B2
Application numberUS-201314096156-A
CountryUS
Kind codeB2
Filing dateDec 4, 2013
Priority dateJul 5, 2012
Publication dateJan 6, 2015
Grant dateJan 6, 2015

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Embodiments of the present invention provide an array of fin-type transistors formed on top of an oxide layer. At least a first and a second of the fin-type transistors have their respective source and drain contacts being formed inside the oxide layer, with one of the contacts of the first fin-type transistor being conductively connected to one of the contacts of the second fin-type transistor by an epitaxial silicon layer, wherein the epitaxial silicon layer is formed on top of a first and a second fin of the first and second fin-type transistors respectively.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor structure comprising: an array of fin-type transistors formed on top of an oxide layer, at least a first and a second of said fin-type transistors having their respective source and drain contacts formed inside openings created in said oxide layer, one of said contacts of said first fin-type transistor being conductively connected to one of said contacts of said second fin-type transistor by an epitaxial silicon layer, said epitaxial silicon…

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Next steps

Free tools are coming soon. Tell us what you want to track and we'll notify you.

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US8928091B2 cover?
Embodiments of the present invention provide an array of fin-type transistors formed on top of an oxide layer. At least a first and a second of the fin-type transistors have their respective source and drain contacts being formed inside the oxide layer, with one of the contacts of the first fin-type transistor being conductively connected to one of the contacts of the second fin-type transistor…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10D86/215. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).