Air gap spacer formation for nano-scale semiconductor devices
US-2024079266-A1 · Mar 7, 2024 · US
US8928091B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928091-B2 |
| Application number | US-201314096156-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 4, 2013 |
| Priority date | Jul 5, 2012 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Embodiments of the present invention provide an array of fin-type transistors formed on top of an oxide layer. At least a first and a second of the fin-type transistors have their respective source and drain contacts being formed inside the oxide layer, with one of the contacts of the first fin-type transistor being conductively connected to one of the contacts of the second fin-type transistor by an epitaxial silicon layer, wherein the epitaxial silicon layer is formed on top of a first and a second fin of the first and second fin-type transistors respectively.
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What is claimed is: 1. A semiconductor structure comprising: an array of fin-type transistors formed on top of an oxide layer, at least a first and a second of said fin-type transistors having their respective source and drain contacts formed inside openings created in said oxide layer, one of said contacts of said first fin-type transistor being conductively connected to one of said contacts of said second fin-type transistor by an epitaxial silicon layer, said epitaxial silicon…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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