Architecture to improve cell size for compact array of split gate flash cell

Patent metadata

Field	Value
Publication number	US-8928060-B2
Application number	US-201313891281-A
Country	US
Kind code	B2
Filing date	May 10, 2013
Priority date	Mar 14, 2013
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing isolated source regions that are diffused only in the active regions between the stacked control gate structures. The architecture contains no CS under the isolation region, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. A metal layer is disposed along the semiconductor body above the common source regions to provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. Hence, this particular architecture reduces the resistance and the metal connection over several cells in an array suppresses the area over head.

First claim

What is claimed is:

1. A memory device comprising:
a first pair of split gate flash memory cells disposed over a semiconductor body, and respectively comprising a stacked gate laterally separated in a first direction from an erase gate by a spacer,
a first shared common source region disposed in the semiconductor body at a first location between the stacked gates of the first pair of split gate flash memory cells, wherein the erase gates of the first pair of split gate flash mem…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Tsair Yong-Shiuan
• Chu Wen-Ting
• Liu Po-Wei
• Huang Wen-Tuo

Classifications

• H10D30/0411 Primary

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L29/788 Primary

  Electricity · mapped topic

• H10B41/00

  Electricity · mapped topic