Structure and method for integrated devices on different substartes with interfacial engineering
US-9362123-B2 · Jun 7, 2016 · US
High-k transistors with low threshold voltage
US8927409B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8927409-B2 |
| Application number | US-201314046218-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 4, 2013 |
| Priority date | Jan 20, 2010 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method for forming a semiconductor structure, the method comprising: forming a high-k dielectric layer over a semiconductor substrate; forming a gate layer over the high-k dielectric layer, wherein the gate layer initially comprises a material selected from the group consisting of: a conductive material, a non-conductive material, and a combination thereof; heating the gate layer to 350° C., wherein, if the gate layer initially includes the non-c…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8927409B2 cover?
- An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D64/01314. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).