Manufacturing process for a 3d assembly

Patent metadata

Field	Value
Publication number	US-2026101588-A1
Application number	US-202519320192-A
Country	US
Kind code	A1
Filing date	Sep 5, 2025
Priority date	Sep 6, 2024
Publication date	Apr 9, 2026
Grant date	—

Abstract

The present description concerns a process including the following steps: providing a plurality of assemblies, each including a donor substrate covered by a functional block successively including a first interconnection layer, a functional layer, and a second interconnection layer, the functional layer including one or more electronic components, the interconnection layers including a dielectric material in which are formed conductive elements, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with a subsequent direct bonding, successively transferring, onto a receiver substrate the functional blocks, by direct bonding, to form a 3D assembly comprising a receiver substrate covered by a stack of two functional blocks.

First claim

1 . Manufacturing process for a 3D assembly comprising the following steps:
providing at least two assemblies, each comprising a donor substrate covered by a functional block successively comprising a first interconnection layer, a functional layer, and a second interconnection layer, the functional layer comprising one or more electronic components, the first interconnection layer and the second interconnection layer comprising a dielectric material in which are formed conductive elements, preferably made of copper, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with a subsequent direct bonding, successively transferring, to a receiver substrate, the functional blocks, by direct bonding, the conductive elements of the first interconnection layer of the first functional block being opposite and in contact with the conductive elements of the second interconnection layer of the second functional block, whereby a 3D assembly comprising a receiver substrate covered by a stack of two functional blocks is obtained.

2 . Method according to claim 1 , wherein at least 5 functional blocks, preferably at least 10 functional blocks, are transferred successively onto the receiver substrate.

3 . Method according to claim 1 , wherein after the transfer of the functional blocks, the method comprises the following steps:
bonding the 3D assembly to an adhesive, cutting the receiver substrate and the functional blocks and removing the receiver substrate, whereby a plurality of stacks of singulated functional blocks are obtained, optionally, bonding the different stacks of singulated functional blocks onto an external element, such as a printed circuit board or a laminated substrate.

4 . Method according to claim 1 , wherein one of the functional blocks partially covers the donor substrate, interconnection blocks being arranged, on the donor substrate, on each side of said functional block and wherein said functional block and the interconnection blocks are transferred simultaneously onto the receiver substrate.

5 . Method according to claim 1 , wherein at least one of the assemblies is obtained according to the following steps:
providing a temporary substrate covered by the functional layer, forming the first interconnection layer on a first surface of the functional layer and planarizing it, transferring the first interconnection layer and the functional layer onto the donor substrate, by bonding the donor substrate to the functional layer and separating the temporary substrate, forming the second interconnection layer on a second surface of the functional layer, planarizing the second interconnection layer.

6 . Process according to claim 1 , wherein part of or all the functional blocks comprise electronic dies.

7 . Process according to claim 1 , wherein the receiver substrate is covered by an interconnection layer comprising a dielectric material in which are formed conductive elements.

8 . Process according to claim 1 , wherein the functional layer has a thickness smaller than 100 μm and, preferably, smaller than 50 μm.

9 . Process according to claim 1 , wherein the bonding energy between the donor substrate and the functional block is smaller than the bonding energy between the functional block and the receiver substrate, or the donor substrate comprises a buried fragile layer.

10 . Process according to claim 1 , wherein the donor substrate is covered by a stack of a plurality of functional blocks, and wherein, during the transfer step, the stack of functional blocks is transferred in a single operation onto the receiver substrate.

11 . Method of determining the steps of a 3D assembly manufacturing process, the determination method comprising the following steps:
defining functions of the 3D assembly, the 3D assembly comprising a substrate and a stack of different functional blocks, each functional block comprising a functional layer, comprising one or more electronic components, arranged between two interconnection layers, the interconnection layers comprising a dielectric material in which are formed conductive elements, preferably made of copper, each functional block being planar, simulating the 3D assembly by selecting different natures and/or dimensions of the substrate and/or of the functional blocks and/or by selecting different stacks of functional blocks, whereby a first manufacturing process for the 3D assembly is selected.

12 . Method according to claim 11 , wherein at least another manufacturing process for the 3D assembly is defined and compared with the first 3D assembly manufacturing process, according to several criteria, for example in terms of feasibility, technical risk, functionality, cost, and/or impact on the environment, so as to select the most suitable 3D assembly manufacturing process.

13 . 3D assembly comprising a receiver substrate on which are stacked at least two functional blocks, preferably at least 5 functional blocks, even more preferably at least 10 functional blocks,
each functional block comprising a functional layer comprising one or more electronic components, arranged between two interconnection layers, the interconnection layers comprising a dielectric material in which are formed conductive elements, preferably made of copper, each functional block being planar.

14 . Assembly according to claim 13 , wherein each functional block comprises an electronic die.

15 . Assembly comprising a donor substrate covered by a functional block successively comprising a first interconnection layer, a functional layer, and a second interconnection layer, the functional layer comprising one or more electronic components, the first interconnection layer and the second interconnection layer comprising a dielectric material in which are formed conductive elements, preferably made of copper, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with a subsequent direct bonding.

Assignees

• Commissariat A Ienergie Atomique Et Aux Energies Alternatives

Inventors

• Beaumont Aurélie

Classifications

• H10P72/7434

  used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10P72/7426

  used as a support during build up manufacturing of active devices · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title