Semiconductor devices

Patent metadata

Field	Value
Publication number	US-2026101520-A1
Application number	US-202519347130-A
Country	US
Kind code	A1
Filing date	Oct 1, 2025
Priority date	Oct 8, 2024
Publication date	Apr 9, 2026
Grant date	—

Abstract

A semiconductor device includes a peripheral circuit structure including a peripheral circuit pattern, a bonding structure including a bonding layer structure, a cell structure including a channel extending in a vertical direction perpendicular to an upper surface of a substrate, a word line at a side of the channel and extending in a first direction parallel to the upper surface of the substrate, a bit line structure at one end of the channel in the vertical direction and extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, and a capacitor at another end of the channel in the vertical direction and electrically connected thereto, a word line wiring structure electrically connecting the peripheral circuit pattern and the word line, and a bit line wiring structure electrically connecting the peripheral circuit pattern and the bit line structure.

First claim

1 . A semiconductor device comprising:
a peripheral circuit structure including a peripheral circuit pattern on a first front surface of a substrate; a bonding structure including a bonding layer structure on the peripheral circuit structure and a bonding pad structure therein; a cell structure on the bonding structure and including
a channel extending in a vertical direction, the vertical direction being perpendicular to an upper surface of the substrate,
a word line at a side of the channel and extending in a first direction, the first direction being parallel to the upper surface of the substrate,
a bit line structure at one end of the channel in the vertical direction and extending in a second direction, the second direction being parallel to the upper surface of the substrate and crossing the first direction, and
a capacitor at another end of the channel in the vertical direction and electrically connected thereto;
a word line wiring structure electrically connecting the peripheral circuit pattern and the word line through a word line contact, the word line contact contacting an upper surface of the bonding pad structure; and a bit line wiring structure electrically connecting the peripheral circuit pattern and the bit line structure through a bit line contact, the bit line contact extending through the bonding layer structure.

2 . The semiconductor device according to claim 1 , wherein
the bonding layer structure includes
a first bonding layer and a second bonding layer sequentially stacked on the peripheral circuit structure, and
the bonding pad structure includes a first bonding pad and a second bonding pad in the first bonding layer and the second bonding layer, respectively, and
a planar area of the first bonding pad or a planar area of the second bonding pad at an interface of the first bonding layer and the second bonding layer is greater than a cross-sectional area of the bit line contact at the interface of the first bonding layer and the second bonding layer.

3 . The semiconductor device according to claim 2 , wherein
the substrate includes a cell array region and an extension region surrounding the cell array region, a plurality of bonding pad structures including the bonding pad structure are spaced apart from each other in the first direction and the second direction on the cell array region of the substrate, and a plurality of bit line contacts including the bit line contact are spaced apart from each other in the first direction and the second direction on the extension region of the substrate.

4 . The semiconductor device according to claim 3 , wherein a number of the plurality of bonding pad structures per unit area at the interface of the first bonding layer and the second bonding layer of the cell array region of the substrate is smaller than a number of the plurality of bit line contacts per unit area at the interface of the first bonding layer and the second bonding layer of the extension region of the substrate.

5 . The semiconductor device according to claim 3 , wherein
the peripheral circuit structure further includes
a plurality of landing pads electrically connected to the peripheral circuit pattern, and
the plurality of landing pads are spaced apart from each other in the first direction, the second direction, and the vertical direction, and
the plurality of bit line contacts extend through the bonding structure and contact upper surfaces of the plurality of landing pads, respectively.

6 . The semiconductor device according to claim 1 , wherein
a surface of the cell structure in the vertical direction adjacent to the capacitor is defined as a second front surface, an opposite surface thereof is defined as a second rear surface, and the second rear surface of the cell structure and the first front surface of the substrate face each other.

7 . The semiconductor device according to claim 6 , wherein an upper surface of the bit line contact is between an upper surface of the channel and a lower surface of the capacitor.

8 . The semiconductor device according to claim 1 , wherein
a surface of the cell structure in the vertical direction adjacent to the capacitor is defined as a second front surface, an opposite surface thereof is defined as a second rear surface, and the second front surface of the cell structure and the first front surface of the substrate face each other.

9 . The semiconductor device according to claim 8 , wherein an upper surface of the bit line contact is higher than an upper surface of the bit line structure based on the first front surface of the substrate.

10 . The semiconductor device according to claim 1 , wherein the bonding pad structure includes copper.

11 . A semiconductor device comprising:
a cell structure including
a channel extending in a first direction,
a word line at a side of the channel and extending in a second direction, the second direction being perpendicular to the first direction;
a bit line structure at one end of the channel in the first direction and extending in a third direction, the third direction being perpendicular to each of the first direction and the second direction, and
a capacitor at another end of the channel in the first direction and electrically connected thereto;
a peripheral circuit structure at a side of the cell structure in the first direction and including a peripheral circuit pattern on a first front surface among the first front surface and a first rear surface of a substrate in the first direction; a bonding structure between the cell structure and the peripheral circuit structure and including a bonding layer structure and a bonding pad structure therein; a word line wiring structure electrically connecting the peripheral circuit pattern and the word line through a word line contact, the word line contact contacting a lower surface of the bonding pad structure; and a bit line wiring structure electrically connecting the peripheral circuit pattern and the bit line structure through a bit line contact, the bit line contact extending through the bonding layer structure.

12 . The semiconductor device according to claim 11 , wherein
the substrate includes a cell array region and an extension region surrounding the cell array region, the bonding layer structure includes a first bonding layer and a second bonding layer sequentially stacked on the peripheral circuit structure, an interface of the first bonding layer and the second bonding layer includes a pad region on the bonding pad structure and a contact region on the bit line contact, and a plurality of bonding pad structures including the bonding pad structure are spaced apart from each other in second and third directions in the pad region, and a plurality of bit line contacts including the bit line contact are spaced apart from each other in the second and third directions in the contact region.

13 . The semiconductor device according to claim 12 , wherein
a plurality of pad regions including the pad region are spaced apart from each other in the second and third directions, a plurality of contact regions including the contact region are spaced apart from each other in the second and third directions, and when viewed from above, the plurality of pad regions and the plurality of contact regions are arranged together in a chess board pattern.

14 . The semiconductor device according to claim 12 , wherein
a plurality of pad regions including the pad region extend in the second direction and are spaced apart from each other in the third direction, a plurality of contact regions including the contact region extend

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hyeonseok
• Kim Minsoo
• Kim Seunghoon
• Kim Yongkwan
• Kim Huijung
• Park Jiho
• Lee Kiseok
• Chae Heejae

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W90/00

  Package configurations · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title