Semiconductor device

Patent metadata

Field	Value
Publication number	US-2026101497-A1
Application number	US-202519331309-A
Country	US
Kind code	A1
Filing date	Sep 17, 2025
Priority date	Oct 8, 2024
Publication date	Apr 9, 2026
Grant date	—

Abstract

A semiconductor device including a bit line extending in a vertical direction on a substrate, a transistor body electrically connected to the bit line and including a first source/drain region, a channel region, and a second source/drain region in a first horizontal direction, a gate electrode extending in a second horizontal direction intersecting the first horizontal direction and on the channel region where a gate dielectric layer is between the gate electrode and the channel region, and a cell capacitor electrically connected to the second source/drain region and including a storage electrode, a capacitor dielectric layer and a plate electrode in the first horizontal direction. A doped polysilicon layer and a contact metal layer are both between the second source/drain region and the storage electrode.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a bit line extending in a vertical direction on a substrate; a transistor body electrically connected to the bit line and including a first source/drain region, a channel region, and a second source/drain region in a first horizontal direction; a gate electrode extending in a second horizontal direction intersecting the first horizontal direction and on the channel region, wherein a gate dielectric layer is between the gate electrode and the channel region; and a cell capacitor electrically connected to the second source/drain region and including a storage electrode, a capacitor dielectric layer and a plate electrode in the first horizontal direction, wherein a doped polysilicon layer and a contact metal layer are both between the second source/drain region and the storage electrode.

2 . The semiconductor device of claim 1 , wherein the doped polysilicon layer, the second source/drain region, and the channel region are in contact with one another, and have respective doping concentrations that vary along the first horizontal direction.

3 . The semiconductor device of claim 2 , wherein the doping concentration of the doped polysilicon layer is greater than the doping concentration of the second source/drain region.

4 . The semiconductor device of claim 3 , wherein a dopant of the doped polysilicon layer is same as a dopant of the second source/drain region.

5 . The semiconductor device of claim 4 , wherein the doped polysilicon layer is doped with an n-type dopant, and
wherein an n-type doping concentration of the doped polysilicon layer is between 1E20 and 5E21 atoms/cm 3 .

6 . The semiconductor device of claim 1 , wherein an area of a first contact surface where the doped polysilicon layer and the second source/drain region are in contact with each other is less than an area of a second contact surface where the doped polysilicon layer and the contact metal layer are in contact with each other and less than an area of a third contact surface where the contact metal layer and the storage electrode are in contact with each other.

7 . The semiconductor device of claim 6 , wherein the doped polysilicon layer has a convex surface that extends toward the second source/drain region.

8 . The semiconductor device of claim 6 , wherein the first contact surface and the third contact surface comprise flat surfaces, and the second contact surface comprises a curved surface.

9 . The semiconductor device of claim 1 , wherein the first source/drain region, the channel region, and the second source/drain region comprise respective single crystal semiconductor materials.

10 . The semiconductor device of claim 1 , wherein the contact metal layer comprises at least one metal comprising titanium (Ti), molybdenum (Mo), tungsten (W), cobalt (Co), tantalum (Ta), ruthenium (Ru), copper (Cu), zirconium (Zr), or nickel (Ni), a metal nitride and/or a metal silicide,
wherein the metal nitride and the metal silicide comprise the at least one metal.

11 . A semiconductor device comprising:
a plurality of transistor bodies spaced apart from one another in a vertical direction on a substrate and extending in parallel in a first horizontal direction, wherein ones of the plurality of transistor bodies comprise a first source/drain region, a channel region, and a second source/drain region; a plurality of gate electrodes spaced apart from one another in the vertical direction, extending in parallel to one another in a second horizontal direction intersecting the first horizontal direction, wherein ones of the plurality of gate electrodes are on at least a top surface and a bottom surface of the channel region of a respective one of the plurality of transistor bodies, and wherein a gate dielectric layer is between the channel region and the ones of the plurality of gate electrodes; a plurality of bit lines spaced apart from one another in the second horizontal direction on the substrate, and extending in parallel in the vertical direction, wherein respective ones of the plurality of bit lines are electrically connected to the first source/drain region of respective ones of the plurality of transistor bodies; and a cell capacitor including a plurality of storage electrodes, a capacitor dielectric layer, and a plate electrode, and electrically connected to the second source/drain region of respective ones of the plurality of transistor bodies, wherein respective ones of a plurality of doped polysilicon layers are between the second source/drain region of respective ones of the plurality of transistor bodies and respective ones of the plurality of storage electrodes.

12 . The semiconductor device of claim 11 , wherein a doping concentration of respective ones of the plurality of doped polysilicon layers is higher than a doping concentration of the second source/drain region of respective ones of the plurality of transistor bodies, and
wherein a dopant of respective ones of the plurality of doped polysilicon layers is same as a dopant of the second source/drain region of respective ones of the plurality of transistor bodies.

13 . The semiconductor device of claim 12 , wherein the dopant of respective ones of the plurality of doped polysilicon layers comprises arsenic (As) or phosphorus (P), and
wherein the doping concentration of respective ones of the plurality of doped polysilicon layers is between 1E20 and 5E21 atoms/cm 3 .

14 . The semiconductor device of claim 11 , wherein respective ones of a plurality of contact metal layers are between respective ones of the plurality of storage electrodes of the cell capacitor and respective ones of the plurality of doped polysilicon layers.

15 . The semiconductor device of claim 14 , wherein an area of a first contact surface where respective ones of the plurality of doped polysilicon layers is in contact with the second source/drain region of respective ones of the plurality of transistor bodies is less than an area of a second contact surface where respective ones of the plurality of doped polysilicon layers is in contact with respective ones of the plurality of contact metal layers, and
wherein the second contact surface comprises a convex surface that extends towards the second source/drain region of respective ones of the plurality of transistor bodies.

16 . A semiconductor device comprising:
a bit line extending in a vertical direction on a substrate; a transistor body electrically connected to the bit line and including a first source/drain region, a channel region, and a second source/drain region in a first horizontal direction; a gate electrode extending in a second horizontal direction intersecting the first horizontal direction and on the channel region, wherein a gate dielectric layer is between the gate electrode and the channel region; a cell capacitor electrically connected to the second source/drain region and including a storage electrode, a capacitor dielectric layer, and a plate electrode in the first horizontal direction; and a doped polysilicon layer and a contact metal layer, both between the second source/drain region and the storage electrode, wherein the second source/drain region has a contact surface with the doped polysilicon layer and has a doping concentration that varies along the first horizontal direction.

17 . The semiconductor device of claim 16 , wherein the doping concentration of the second source/drain region decreases as a distance from the doped polysilicon layer increases.

18 . The semiconductor dev

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seokwon
• Lee Jungha
• Park Sanghyun
• Lee Dosun
• Lee Sunjung
• Lee Jongwon

Classifications

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/48

  Data lines or contacts therefor · CPC title

• H10B12/30 Primary

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title