Integrated circuit packages including a heat spreader having a high thermal conductivity material in 3 dimensional die stacks

Patent metadata

Field	Value
Publication number	US-2026090451-A1
Application number	US-202418895544-A
Country	US
Kind code	A1
Filing date	Sep 25, 2024
Priority date	Sep 25, 2024
Publication date	Mar 26, 2026
Grant date	—

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die electrically coupled to the first die; a dielectric material, around the second die and the third die, having a non-planar surface; a first material, on the non-planar surface of the dielectric material and on the second die and the third die, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns; a second material, on the first material, including titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, or silicon, carbon, and nitrogen; and a third material, on the second material, having a thermal conductivity greater than 150 W/m-K and a thickness between 1 micron and 200 microns.

First claim

1 . A microelectronic assembly, comprising:
a first die having a surface; a second die having a first surface and an opposing second surface, wherein the first surface of the second die is electrically coupled to the surface of the first die; a third die having a first surface and an opposing second surface, wherein the first surface of the third die is electrically coupled to the surface of the first die; a dielectric material on the surface of the first die and around and between the second die and the third die, the dielectric material having a non-planar surface; a layer on the non-planar surface of the dielectric material and with the second surface of the second die and the second surface of the third die, the layer including:
a first material having a thermal conductivity equal to or greater than 10 watt per meter-kelvin (W/m-K) and having a thickness on the second surfaces of the second die and the third die between 1 micron and 2 microns; and
a second material, on the first material, the second material including one or more of titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, and silicon, carbon, and nitrogen; and
a third material, on the second material of the layer, having a thermal conductivity equal to or greater than 150 watt per meter-kelvin (W/m-K) and the third material having a thickness between 1 micron and 200 microns.

2 . The microelectronic assembly of claim 1 , wherein the dielectric material includes silicon and nitrogen, silicon and oxygen, or silicon, nitrogen, and carbon; a polymer material; a mold material; or a low-k or ultra low-k dielectric.

3 . The microelectronic assembly of claim 1 , wherein the first material includes one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, and boron and arsenic.

4 . The microelectronic assembly of claim 1 , wherein the third material includes one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, boron and arsenic, silver, and gold.

5 . The microelectronic assembly of claim 1 , wherein the second material has a thickness between 0.2 nanometers and 100 nanometers.

6 . The microelectronic assembly of claim 1 , wherein the layer further comprises:
a fourth material between the first material and the non-planar surface of the dielectric material and the second surfaces of the second die and the third die, the fourth material including titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, or tungsten.

7 . The microelectronic assembly of claim 1 , further comprising:
a substrate on the third material, wherein a material of the substrate includes silicon.

8 . The microelectronic assembly of claim 7 , wherein a crystalline structure of the third material and a crystalline structure of the material of the substrate are a same crystalline structure.

9 . The microelectronic assembly of claim 8 , wherein the crystalline structure has a (111) orientation.

10 . A microelectronic assembly, comprising:
a first die having a surface; a second die having a first surface and an opposing second surface, wherein the first surface of the second die is electrically coupled to the surface of the first die; a third die having a first surface and an opposing second surface, wherein the first surface of the third die is electrically coupled to the surface of the first die; a dielectric material on the surface of the first die and around and between the second die and the third die, the dielectric material having a non-planar surface; a first material on the non-planar surface of the dielectric material and on the second surfaces of the second die and the third die, the first material having a thermal conductivity equal to or greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns; a second material, on the first material, the second material including one or more of titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, and silicon, carbon, and nitrogen; and a third material, on a portion of the second material, wherein the third material is on the second surface of the second die and not on the second surface of the third die, and wherein the third material has a thermal conductivity equal to or greater than 150 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 200 microns.

11 . The microelectronic assembly of claim 10 , wherein the first material includes one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, and boron and arsenic.

12 . The microelectronic assembly of claim 10 , wherein the third material includes one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, boron and arsenic, silver, and gold.

13 . The microelectronic assembly of claim 10 , wherein the second material has a thickness between 0.2 nanometers and 100 nanometers.

14 . The microelectronic assembly of claim 10 , further comprising:
a fourth material between the second material and the third material on the second surface of the second die, wherein an interface between the fourth material and the third material is non-planar.

15 . The microelectronic assembly of claim 14 , wherein the fourth material includes copper or aluminum.

16 . A microelectronic assembly, comprising:
a first layer including a first die; a second layer, on the first layer, including second dies and a first dielectric material around and between the second dies, and wherein a surface of the first dielectric material has an inconsistent topography, and wherein the first die is electrically coupled to the second dies by interconnects having a pitch of less than 10 microns between adjacent interconnects; a third layer, on the second layer, including:
a first material having a thermal conductivity equal to or greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns; and
a second material, on the first material, the second material including one or more of titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, and silicon, carbon, and nitrogen;
a fourth layer, on the third layer, including a third material having a thermal conductivity equal to or greater than 150 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 200 microns; and a fifth layer, on the fourth layer, including third dies and a second dielectric material around and between the third dies, and wherein a surface of the second dielectric material has an inconsistent topography.

17 . The microelectronic assembly of claim 16 , wherein the first material includes one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, and boron and arsenic.

18 . The microelectronic assembly of claim 16 , wherein the third material includes one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, boron and arsenic, silver, and gold.

19 . The microelectronic assembly of claim 16 , wherein the second material has a thickness between 0.2 nanometers and 100 nanometers.

20 . The microelectronic assembly of claim 16 , further comprising:
a via extending through the first material, the second material, and the third material, wherein the via includes a conductive mat

Assignees

• Intel Corp

Inventors

• Sounart Thomas
• Li Wenhao
• Eid Feras
• Vyatskikh Andrey
• Dogiamis Georgios
• Talukdar Tushar

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title