Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-2026089953-A1
Application number	US-202519403634-A
Country	US
Kind code	A1
Filing date	Nov 28, 2025
Priority date	Feb 6, 2023
Publication date	Mar 26, 2026
Grant date	—

Abstract

A semiconductor device includes a first gate structure including a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked; an isolation insulating layer located in the first gate structure, the isolation insulating layer including a first line portion extending in a first direction, a plurality of first protrusions protruding from the first line portion towards one side of the first line portion in a second direction, and a plurality of second protrusions protruding from the first line portion towards another side of the first line portion in an opposite direction to the first protrusions, wherein the second direction is orthogonal to the first direction; a plurality of first memory patterns, wherein one of the plurality of first memory patterns surrounds one of the plurality of first protrusions; and a plurality of first passivation patterns, wherein one of the plurality of first passivation patterns is located between the first line portion and one of the plurality of first memory patterns.

First claim

What is claimed is:

1 . A manufacturing method of a semiconductor device, the manufacturing method comprising:
forming a stack including a plurality of first material layers and a plurality of second material layers that are alternately stacked; forming, in the stack, an opening including a plurality of first regions, each having a first width, and a plurality of second regions, each having a second width that is less than the first width; forming, in the opening, a memory layer having different thicknesses in the first region compared to the second region; forming a plurality of memory patterns located in the first regions by etching the memory layer; forming a plurality of passivation patterns on etched surfaces of the plurality of memory patterns; and forming an isolation insulating layer in the opening.

2 . The manufacturing method of claim 1 , wherein the forming of the plurality of memory patterns comprises:
forming a memory layer having a first thickness in the plurality of first regions and a second thickness that is less than the first thickness in the plurality of second regions; and forming the plurality of memory patterns by etching a portion of the memory layer formed in the plurality of second regions.

3 . The manufacturing method of claim 1 , further comprising:
forming, in the memory layer, a channel layer having a first thickness in the plurality of first regions and a second thickness that is less than the first thickness in the plurality of second regions; and forming a plurality of channel patterns located in the plurality of first regions by removing a portion of the channel layer formed in the plurality of second regions.

4 . The manufacturing method of claim 3 , wherein one of the plurality of passivation patterns extends to an etched surface of one of the plurality of channel patterns.

5 . The manufacturing method of claim 3 , further comprising:
forming a passivation layer by oxidizing the plurality of memory patterns and the plurality of channel patterns; and forming the plurality of passivation patterns by etching the passivation layer.

6 . The manufacturing method of claim 5 , wherein the passivation layer is formed on the etched surfaces of the plurality of memory patterns, etched surfaces of the plurality of channel patterns, and inner surfaces of the plurality of channel patterns, and
wherein, when the passivation layer is etched, a portion of the passivation layer formed on the inner surfaces of the plurality of channel patterns is removed.

7 . The manufacturing method of claim 1 , wherein, in the forming of the plurality of passivation patterns, the plurality of passivation patterns are formed by oxidizing the etched surfaces of the plurality of memory patterns.

8 . The manufacturing method of claim 1 , further comprising:
replacing the plurality of first material layers exposed between the plurality of passivation patterns with a plurality of third material layers.

9 . A manufacturing method of a semiconductor device, the manufacturing method comprising:
forming a stack including a plurality of first material layers and a plurality of second material layers that are alternately stacked; forming a plurality of first openings in the stack; forming a second opening connecting the first openings to each other by expanding the first openings; forming a plurality of mutually isolated channel patterns in the second opening; forming a plurality of memory patterns in the second opening, wherein one of the plurality of memory patterns surrounds one of the plurality of channel patterns; forming, in the second opening, a plurality of passivation patterns extending from a side wall of a memory pattern, among the plurality of memory patterns, to a side wall of a channel pattern, among the plurality of channel patterns; and replacing the plurality of first material layers exposed between the plurality of passivation patterns with a plurality of third material layers through the second opening.

10 . The manufacturing method of claim 9 , wherein the forming of the plurality of memory patterns comprises:
forming, in the second opening, a memory layer having varying thicknesses; and forming the plurality of memory patterns by etching the memory layer.

11 . The manufacturing method of claim 10 , wherein the forming of the plurality of channel patterns comprises:
forming, in the memory layer, a channel layer having varying thicknesses; and forming the plurality of channel patterns by etching the channel layer.

12 . The manufacturing method of claim 11 , wherein the forming of the plurality of passivation patterns comprises:
forming a passivation layer by oxidizing the plurality of memory patterns and the plurality of channel patterns exposed through the second opening; and forming the plurality of passivation patterns by etching the passivation layer.

13 . The manufacturing method of claim 9 , further comprising:
forming an isolation insulating layer in the second opening.

14 . The manufacturing method of claim 9 , further comprising:
forming a plurality of third openings in the stack; forming a fourth opening connecting the third openings to each other by expanding the plurality of third openings; forming a dummy memory layer in the fourth opening; and forming a dummy channel layer in the dummy memory layer.

15 . The manufacturing method of claim 14 , wherein the plurality of third openings are formed when the plurality of first openings are formed, and
wherein the fourth opening is formed when the second opening is formed.

16 . The manufacturing method of claim 14 , wherein the fourth opening is located at a boundary between memory blocks.

Assignees

• Sk Hynix Inc

Inventors

• Kwak Rho Gyu
• Jang Jung Shik
• Park In Su
• Choi Seok Min
• Choi Won Geun
• Choi Jung Dal

Classifications

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title