Memory device and driving method thereof

Patent metadata

Field	Value
Publication number	US-2026089949-A1
Application number	US-202519172171-A
Country	US
Kind code	A1
Filing date	Apr 7, 2025
Priority date	Sep 25, 2024
Publication date	Mar 26, 2026
Grant date	—

Abstract

A memory device includes a substrate, a channel layer on one surface of the substrate and including a semiconductor oxide, a gate electrode between the substrate and the channel layer, a reservoir layer between the channel layer and the gate electrode, an electrolyte layer between the channel layer and the reservoir layer, and a gate oxide layer between the gate electrode and the reservoir layer, wherein the reservoir layer is capable of transferring oxygen vacancies therein to the channel layer or receiving oxygen vacancies transferred from the channel layer depending on a voltage applied to the gate electrode, and a thickness of the electrolyte layer is less than 5 nm.

First claim

What is claimed is:

1 . A memory device comprising:
a substrate; a channel layer on one surface of the substrate, the channel layer including a semiconductor oxide; a gate electrode between the substrate and the channel layer; a reservoir layer disposed the channel layer and the gate electrode; an electrolyte layer between the channel layer and the reservoir layer; and a gate oxide layer between the gate electrode and the reservoir layer, wherein the reservoir layer is capable of transferring oxygen vacancies therein to the channel layer or receiving oxygen vacancies transferred from the channel layer, depending on a voltage applied to the gate electrode, and a thickness of the electrolyte layer is less than 5 nm.

2 . The memory device of claim 1 , wherein
when a first direction refers to a direction parallel to the one surface of the substrate, the channel layer extends along a second direction intersecting the first direction, the gate electrode surrounds at least a portion of the channel layer.

3 . The memory device of claim 2 , further comprising:
a source electrode and a drain electrode electrically connected to the channel layer, wherein the source electrode and the drain electrode are spaced apart from each other based on the second direction.

4 . The memory device of claim 2 , further comprising:
an insulating layer overlapping the gate electrode in at least a partial region when viewed in the second direction, the insulating layer surrounding at least a portion of the channel layer.

5 . The memory device of claim 4 , wherein
the gate electrode includes a plurality of gate electrodes, an adjacent pair of the plurality of gate electrodes are spaced apart from each other based on the second direction, and the insulating layer fills a space between the adjacent pair of the plurality of gate electrodes.

6 . The memory device of claim 1 , wherein the channel layer is parallel to the substrate.

7 . The memory device of claim 6 , further comprising:
a source electrode and a drain electrode electrically connected to the channel layer, wherein the source electrode and the drain electrode are spaced apart from each other based on a first direction parallel to the one surface of the substrate.

8 . The memory device of claim 1 , wherein the reservoir layer is capable of transferring the oxygen vacancies to the channel layer when a positive voltage is applied to the gate electrode, and receiving the oxygen vacancies from the channel layer when a negative voltage is applied to the gate electrode.

9 . The memory device of claim 1 , wherein a sum of thicknesses of the reservoir layer, the electrolyte layer, and the gate oxide layer is 30 nanometers (nm) or less.

10 . The memory device of claim 1 , wherein a ratio (T 1 /T 2 ) of a thickness (T 1 ) of the electrolyte layer and a sum (T 2 ) of thicknesses of the reservoir layer, the electrolyte layer, and the gate oxide layer is 0.3 or less.

11 . The memory device of claim 1 , wherein the thickness of the electrolyte layer is thinner than a thickness of the reservoir layer.

12 . The memory device of claim 1 , wherein the reservoir layer and the electrolyte layer each independently include an oxide having a metal element-oxygen bond including one or more selected from the group of metal elements consisting of hafnium (Hf), cerium (Ce), tantalum (Ta), gallium (Ga), nickel (Ni), aluminum (Al), zinc (Zn), tungsten (W), vanadium (V), titanium (Ti), niobium (Nb), silicon (Si), germanium (Ge), arsenic (As), tellurium (Te), antimony (Sb), indium (In), zirconium (Zr), and tin (Sn).

13 . The memory device of claim 1 , wherein the gate oxide layer includes an oxide having a metal element-oxygen bond including one or more selected from the group of metal elements consisting of tantalum (Ta), hafnium (Hf), aluminum (Al), zinc (Zn), tungsten (W), vanadium (V), titanium (Ti), niobium (Nb), germanium (Ge), arsenic (As), tellurium (Te), antimony (Sb), gallium (Ga), indium (In), zirconium (Zr), tin (Sn), and nickel (Ni).

14 . The memory device of claim 1 , wherein the channel layer includes a semiconductor oxide including one or more selected from the group consisting of tantalum (Ta), hafnium (Hf), aluminum (Al), zinc (Zn), tungsten (W), vanadium (V), titanium (Ti), niobium (Nb), silicon (Si), germanium (Ge), arsenic (As), tellurium (Te), antimony (Sb), gallium (Ga), indium (In), zirconium (Zr), tin (Sn), and nickel (Ni).

15 . The memory device of claim 14 , wherein the channel layer includes one or more selected from the group consisting of indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO), tungsten oxide (WO), indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), magnesium zinc oxide (MgZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaSiO).

16 . The memory device of claim 1 , wherein an oxygen concentration of the electrolyte layer is higher than an oxygen concentration of the reservoir layer.

17 . A method of driving a memory device, the memory device including a substrate, a channel layer on one surface of the substrate and including a semiconductor oxide, a gate electrode between the substrate and the channel layer, a reservoir layer between the channel layer and the gate electrode, an electrolyte layer between the channel layer and the reservoir layer and having a thickness of less than 5 nm, and a gate oxide layer between the gate electrode and the reservoir layer, the method comprising, the method comprising:
transferring oxygen vacancies present in the reservoir layer to the channel layer or transferring oxygen vacancies present in the channel layer to the gate electrode when a voltage is applied to the gate electrode such that an electrical conductivity and a threshold voltage (V th ) of the channel layer change values different from the electrical conductivity and the threshold voltage (V th ) of the channel layer prior to the application of the voltage to the gate electrode, and performing a write operation or an erase operation as the electrical conductivity and the threshold voltage of the channel layer changes.

18 . The method of claim 17 , wherein when the voltage is applied to the gate electrode, the write operation or the erase operation is performed as the threshold voltage (V th ) changes.

19 . The method of claim 17 , wherein
the write operation is performed to transfer the oxygen vacancies present in the reservoir layer to the channel layer by applying a positive voltage to the gate electrode so that the electrical conductivity of the channel layer increases or the threshold voltage (V th ) decreases compared to the electrical conductivity and the threshold voltage (V th ) of the channel layer prior to the application of the voltage to the gate electrode, or the erase operation is performed to transfer the oxygen vacancies present in the channel layer to the reservoir layer by applying a negative voltage to the gate electrode so that the electrical conducti

Assignees

• Samsung Electronics Co Ltd
• Ulsan Nat Inst Science & Tech Unist

Inventors

• Park Garam
• Yoon Tae-Sik
• Han Jimin
• Kim Yumin
• Lee Minhyun
• Hyun Seung Dam
• Noh Taeyun
• Jeong Boyoung

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title