High Critical Temperature Device with Metal Nitride Layer

US2026082819A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2026082819-A1
Application numberUS-202418829562-A
CountryUS
Kind codeA1
Filing dateSep 10, 2024
Priority dateFeb 21, 2020
Publication dateMar 19, 2026
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of fabricating a device including a superconductive layer includes depositing a seed layer on a substrate, exposing the seed layer to an oxygen-containing gas or plasma to form a modified seed layer, and after exposing the seed layer to the oxygen-containing gas or plasma depositing a metal nitride superconductive layer directly on the modified seed layer. The seed layer is a nitride of a first metal, and the superconductive layer is a nitride of a different second metal.

First claim

Opening claim text (preview).

What is claimed is: 1 . A superconducting device, comprising: a dielectric or semiconductor substrate; an oxynitride seed layer disposed on the substrate, the oxynitride seed layer being an oxynitride of a first metal; a metal nitride superconductive layer disposed directly on the seed layer and patterned to form a wire, the metal nitride superconductive being a nitride of a different second metal, wherein the second metal is niobium, titanium, or an alloy of niobium and titanium; and a capping layer of amorphous silicon, an oxide, or a metal nitride which is a nitride of silicon, of the first metal or of a different third metal. 2 . The device of claim 1 , wherein the second metal is niobium. 3 . The device of claim 2 , wherein the first metal is aluminum. 4 . The device of claim 1 , wherein the first metal is aluminum. 5 . The device of claim 1 , wherein the oxynitride seed layer has a thickness of 1-3 nm. 6 . The device of claim 5 , wherein the metal nitride superconductive layer has a thickness of 4-50 nm. 7 . The device of claim 1 , wherein the capping layer is an oxide of the first metal. 8 . The device of claim 7 , wherein the first metal is aluminum. 9 . The device of claim 1 , wherein the capping layer is an oxide of the first metal. 10 . The device of claim 9 , wherein the first metal is aluminum. 11 . The device of claim 1 , wherein the capping layer is silicon oxide or silicon nitride. 12 . The device of claim 1 , wherein the capping layer is a nitride of the different third metal. 13 . The device of claim 1 , wherein the capping layer is amorphous silicon. 14 . The device of claim 1 , wherein the wires have a width of 25 to 250 nm. 15 . The device of claim 1 , wherein trenches through the metal nitride superconductive layer to form the wires do not extend into the seed layer. 16 . The device of claim 1 , wherein trenches through the metal nitride superconductive layer to form the wires also extend into the seed layer. 17 . The device of claim 1 , wherein trenches through the capping layer and through the metal nitride superconductive layer to form the wires.

Assignees

Inventors

Classifications

  • of devices comprising Nb or an alloy of Nb with one or more of the elements of group IVB, e.g. titanium, zirconium or hafnium · CPC title

  • of devices comprising nitrides or carbonitrides · CPC title

  • Reactive sputtering · CPC title

  • Oxidation · CPC title

  • using ionised gases, e.g. ionitriding · CPC title

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What does patent US2026082819A1 cover?
A method of fabricating a device including a superconductive layer includes depositing a seed layer on a substrate, exposing the seed layer to an oxygen-containing gas or plasma to form a modified seed layer, and after exposing the seed layer to the oxygen-containing gas or plasma depositing a metal nitride superconductive layer directly on the modified seed layer. The seed layer is a nitride o…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10N60/0241. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Mar 19 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).