Methods of reducing parasitic capacitance in semiconductor devices

Patent metadata

Field	Value
Publication number	US-2026082676-A1
Application number	US-202519398895-A
Country	US
Kind code	A1
Filing date	Nov 24, 2025
Priority date	Aug 31, 2018
Publication date	Mar 19, 2026
Grant date	—

Abstract

A semiconductor structure includes a source/drain feature, a gate structure disposed adjacent to the source/drain feature, a source/drain contact disposed over and electrically connected to the source/drain feature, an interlayer dielectric (ILD) layer over the source/drain feature and adjacent to the source/drain contact and the gate structure, and an air gap surrounding the source/drain contact and separating the source/drain contact from the ILD layer and the gate structure in a top view.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a source/drain feature; a gate structure disposed adjacent to the source/drain feature; a source/drain contact disposed over and electrically connected to the source/drain feature; an interlayer dielectric (ILD) layer over the source/drain feature and adjacent to the source/drain contact and the gate structure; and an air gap surrounding the source/drain contact and separating the source/drain contact from the ILD layer and the gate structure in a top view.

2 . The semiconductor structure of claim 1 , further comprising a sealing layer above the air gap,
wherein in the top view, the sealing layer surrounds the source/drain contact.

3 . The semiconductor structure of claim 1 , wherein the source/drain feature is a first source/drain feature,
wherein the semiconductor structure further comprises a second source/drain feature, wherein the source/drain contact is further disposed over the second source/drain feature.

4 . The semiconductor structure of claim 1 , wherein the air gap comprises a portion between the gate structure and the source/drain feature.

5 . The semiconductor structure of claim 1 , wherein the air gap comprises a portion between the ILD layer and the source/drain feature.

6 . The semiconductor structure of claim 1 , wherein the air gap comprises a portion between the ILD layer and the gate structure.

7 . The semiconductor structure of claim 1 , further comprising a gate spacer on a sidewall of the gate structure and exposed to the air gap.

8 . The semiconductor structure of claim 1 , wherein the ILD layer is a first ILD layer,
wherein the semiconductor structure further comprises a second ILD layer over the first ILD layer and the gate structure, wherein the air gap comprises a portion between the second ILD layer and the source/drain contact.

9 . A semiconductor structure, comprising:
an epitaxial feature; a gate structure adjacent to the epitaxial feature; a contact feature over and electrically connected to the epitaxial feature and on a side of the gate structure; an interlayer dielectric (ILD) layer over the epitaxial feature and on the side of the gate structure; and an air gap comprising a first portion between the gate structure and the epitaxial feature, a second portion between the ILD layer and the gate structure, and a third portion between the gate structure and the contact feature.

10 . The semiconductor structure of claim 9 , wherein the ILD layer is a first ILD layer,
wherein the semiconductor structure further comprises a second ILD layer over the first ILD layer and the gate structure, wherein the air gap comprises a fourth portion between the second ILD layer and the contact feature.

11 . The semiconductor structure of claim 10 , further comprising a sealing layer between the second ILD layer and the contact feature and above the air gap.

12 . The semiconductor structure of claim 9 , wherein the air gap comprises a fourth portion between the epitaxial feature and the ILD layer.

13 . The semiconductor structure of claim 9 , wherein the epitaxial feature is a first epitaxial feature,
wherein the semiconductor structure further comprises a second epitaxial feature on the side of the gate structure, wherein the contact feature extends to be over the second epitaxial feature.

14 . The semiconductor structure of claim 9 , wherein the air gap comprises a fourth portion exposing a bottom surface of the contact feature.

15 . The semiconductor structure of claim 9 , further comprising a semiconductor layer below the gate structure,
wherein the semiconductor layer is connected to the epitaxial feature.

16 . The semiconductor structure of claim 9 , wherein the contact feature comprises a silicide layer and a conductive layer over the silicide layer,
wherein a middle portion of the silicide layer contacts the epitaxial feature and a side portion of the silicide layer is spaced apart from the epitaxial feature.

17 . A semiconductor structure, comprising:
a first active region comprising a first source/drain feature; a second active region comprising a second source/drain feature; a gate structure over the first active region and the second active region and adjacent to the first source/drain feature and the second source/drain feature, wherein the first source/drain feature and the second source/drain feature are on a same side of the gate structure; a conductive contact disposed over and electrically connected to the first source/drain feature and the second source/drain feature; an air gap comprising a first portion around the conductive contact; and a sealing layer over the air gap and surrounding the conductive contact in a top view.

18 . The semiconductor structure of claim 17 , wherein the air gap comprises a second portion between the gate structure and the first source/drain feature.

19 . The semiconductor structure of claim 17 , wherein a portion of a bottom surface of the conductive contact is exposed to the air gap.

20 . The semiconductor structure of claim 17 , further comprising a dielectric layer over the gate structure,
wherein the sealing layer comprises a portion between the dielectric layer and the conductive contact.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Chen Yen-Ming
• Yang Feng-Cheng
• Yeong Sai-Hooi

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10D84/834

  comprising FinFETs · CPC title