Semiconductor devices including source/drain layers and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2026082634-A1
Application number	US-202519399506-A
Country	US
Kind code	A1
Filing date	Nov 24, 2025
Priority date	Jun 30, 2021
Publication date	Mar 19, 2026
Grant date	—

Abstract

A semiconductor device includes first and second channels, first and second gate structures, first and second source/drain layers, first and second fin spacers, and first and second etch stop patterns. The first channels are disposed vertically on a first region of a substrate. The second channels are disposed vertically on a second region of the substrate. The first gate structure is formed on the first region and covers the first channels. The second gate structure is formed on the second region and covers the second channels. The first and second source/drain layers contact the first and second channels, respectively. The first and second fin spacers contact sidewalls and upper surfaces of the first and second source/drain layers, respectively. The first and second etch stop patterns are formed on the first and second fin spacers, respectively, and do not contact the first and second source/drain layers, respectively.

First claim

1 .- 66 . (canceled)

67 . A method of manufacturing a semiconductor device, the method comprising:
forming a first stack structure on a substrate, the first stack structure including first sacrificial lines and first semiconductor lines alternately and repeatedly stacked; forming a dummy gate structure on the substrate, the dummy gate structure partially covering the first stack structure; forming a first gate spacer and a first sacrificial gate spacer on a sidewall of the dummy gate structure; etching the first stack structure using the dummy gate structure, the first gate spacer and the first sacrificial gate spacer as an etching mask to form a first opening exposing an upper surface of the substrate; performing a first cleansing process on the first opening; forming a first source/drain layer on the exposed upper surface of the substrate; removing the first sacrificial gate spacer; removing the dummy gate structure and the first sacrificial lines to form second and third openings, respectively; and forming a gate structure in the second and third openings, wherein the first sacrificial gate spacer includes silicon nitride, and wherein the first sacrificial gate spacer is not removed during the first cleansing process.

68 . The method of claim 67 , wherein the first cleansing process includes a wet etching process using hydrofluoric acid.

69 . The method of claim 67 , wherein removing the first sacrificial gate spacer includes performing a wet etching process using phosphoric acid.

70 . The method of claim 67 , wherein forming the first gate spacer and the first sacrificial gate spacer includes:
sequentially stacking a spacer layer and a sacrificial layer on the dummy gate structure and the first stack structure; and anisotropically etching the sacrificial layer and the spacer layer.

71 . The method of claim 70 , wherein anisotropically etching the sacrificial layer and the spacer layer includes forming a fin spacer and a sacrificial fin spacer on a sidewall of a portion of the first stack structure that is not covered by the dummy gate structure.

72 . The method of claim 71 , wherein removing the first sacrificial gate spacer includes removing the sacrificial fin spacer.

73 . The method of claim 67 , further comprising, after removing the first sacrificial gate spacer, forming an etch stop layer on the dummy gate structure, the first gate spacer and the first source/drain layer.

74 . The method of claim 67 , further comprising, after forming the first source/drain layer, forming a capping layer on the first source/drain layer by performing a selective deposition process.

75 . The method of claim 67 , wherein:
the substrate includes first and second regions, and the first stack structure, the first gate spacer and the first sacrificial gate spacer are formed on the first region of the substrate, the method further comprises, prior to forming the dummy gate structure, forming a second stack structure on the second region of the substrate, the second stack structure including second sacrificial lines and second semiconductor lines alternately and repeatedly stacked, and the dummy gate structure partially covers the second stack structure.

76 . The method of claim 75 , further comprising, prior to forming the first gate spacer and the first sacrificial gate spacer:
forming a second gate spacer and a second sacrificial gate spacer on a sidewall of a portion of the dummy gate structure on the second region of the substrate; etching the second stack structure using the portion of the dummy gate structure on the second region of the substrate, the second gate spacer and the second sacrificial gate spacer as an etching mask to form a fourth opening exposing an upper surface of the substrate; performing a second cleansing process on the fourth opening; forming a second source/drain layer on the exposed upper surface of the substrate; and removing the second sacrificial gate spacer.

77 . The method of claim 76 , wherein forming the second gate spacer and the second sacrificial gate spacer includes:
sequentially stacking a spacer layer and a second sacrificial spacer layer on the dummy gate structure and the second stack structure; and anisotropically etching the second sacrificial spacer layer and the spacer layer on the second region of the substrate.

78 . The method of claim 77 , wherein forming the first gate spacer and the first sacrificial gate spacer further includes, after removing the second sacrificial gate spacer:
forming a first sacrificial spacer layer on the spacer layer; and anisotropically etching the first sacrificial spacer layer and the spacer layer on the first region of the substrate.

79 . The method of claim 75 , wherein the second sacrificial gate spacer includes silicon nitride, and
wherein the second sacrificial gate spacer is not removed during the second cleansing process.

80 . The method of claim 75 , further comprising, prior to forming the first gate spacer and the first sacrificial gate spacer:
forming a second gate spacer and a second sacrificial gate spacer on a sidewall of a portion of the dummy gate structure on the second region of the substrate; etching the second stack structure using the portion of the dummy gate structure on the second region of the substrate, the second gate spacer and the second sacrificial gate spacer as an etching mask to form a fourth opening exposing an upper surface of the substrate; performing a second cleansing process on the fourth opening; and forming a second source/drain layer on the exposed upper surface of the substrate, wherein the second sacrificial gate spacer is removed during the second cleansing process.

81 . A method of manufacturing a semiconductor device, the method comprising:
forming first and second stack structures on a substrate, the substrate including first and second regions, the first stack structure including first sacrificial lines and first semiconductor lines alternately and repeatedly stacked on the first region of the substrate, and the second stack structure including second sacrificial lines and second semiconductor lines alternately and repeatedly stacked on the second region of the substrate; forming first and second dummy gate structures on the first and second regions of the substrate, respectively, to partially cover the first and second stack structures, respectively; forming a first gate spacer and a first sacrificial gate spacer on a sidewall of the first dummy gate structure; etching the first stack structure using the first dummy gate structure, the first gate spacer and the first sacrificial gate spacer as an etching mask to form a first opening exposing an upper surface of the substrate; performing a first cleansing process on the first opening; forming a first source/drain layer on the exposed upper surface of the substrate; removing the first sacrificial gate spacer; forming a second gate spacer and a second sacrificial gate spacer on a sidewall of the second dummy gate structure; etching the second stack structure using the second dummy gate structure, the second gate spacer and the second sacrificial gate spacer as an etching mask to form a second opening exposing an upper surface of the substrate; performing a second cleansing process on the second opening; forming a second source/drain layer on the exposed upper surface of the substrate; removing the second sacrificial gate spacer; removing the first dummy gate structure and the first sacrificial lines to form second and third openings, respectively; removing th

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Haejun
• Choi Kyungin
• Kim Sungmin
• Lee Seunghun
• Kim Jinbum

Classifications

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title