Memory system, semiconductor device and fabrication method therefor

Patent metadata

Field	Value
Publication number	US-2026082563-A1
Application number	US-202519394751-A
Country	US
Kind code	A1
Filing date	Nov 19, 2025
Priority date	Sep 23, 2022
Publication date	Mar 19, 2026
Grant date	—

Abstract

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of conductive layers and insulating layers stacked alternatingly in a first direction. The stack of conductive layers and insulating layers has a first side and a second side in the first direction. The semiconductor device then includes a semiconductor layer at the first side of the stack of conductive layers and insulating layers, and a first isolation structure extending through, in the first direction, the semiconductor layer and a subset of the stack of conductive layers and insulating layers. The subset of the stack of conductive layers and insulating layers includes a first conductive layer. The first isolation structure separates a first portion of the first conductive layer from a second portion of the first conductive layer.

First claim

What is claimed is:

1 . A method for fabricating a semiconductor device, comprising:
forming a stack of conductive layers and insulating layers that are stacked alternatingly in a first direction, the stack of conductive layers and insulating layers having a first side and a second side in the first direction; forming a semiconductor layer at the first side of the stack of conductive layers and insulating layers; and forming a first isolation structure that extends through, in the first direction, the semiconductor layer and a subset of the stack of conductive layers and insulating layers, the subset of the stack of conductive layers and insulating layers comprising a first conductive layer, the first isolation structure separating a first portion of the first conductive layer from a second portion of the first conductive layer.

2 . The method of claim 1 , further comprising:
forming a first gate line slit (GLS) structure and a second GLS structure that extend through the stack of conductive layers and insulating layers in the first direction, the first GLS structure and the second GLS structure being parallel in a second direction that is perpendicular to the first direction, wherein the first isolation structure is between the first GLS structure and the second GLS structure and is parallel to the first GLS structure and the second GLS structure.

3 . The method of claim 2 , further comprising:
forming a second isolation structure that extends through, in the first direction, the semiconductor layer and the subset of the stack of conductive layers and insulating layers between the first GLS structure and the second GLS structure, wherein the second isolation structure and the first isolation structure are between the first GLS structure and the second GLS structure and are parallel to the first GLS structure and the second GLS structure.

4 . The method of claim 1 , wherein the forming the first isolation structure comprises:
forming a trench in the semiconductor layer and the subset of the stack of conductive layers and insulating layers; and filling the trench with insulating material.

5 . The method of claim 4 , wherein the forming the trench comprises:
performing a first etching process that creates an opening in the semiconductor layer and the subset of the stack of conductive layers and insulating layers in the first direction; and performing a second etching process that recesses the first conductive layer based on the opening.

6 . The method of claim 4 , wherein the filling the trench with the insulating material comprises:
depositing the insulating material using atomic layer deposition (ALD).

7 . The method of claim 1 , wherein the forming the semiconductor layer comprises:
removing an initial stack of layers from the first side of the stack of conductive layers and insulating layers; and depositing the semiconductor layer at the first side of the stack of conductive layers and insulating layers.

8 . The method of claim 7 , wherein the depositing the semiconductor layer comprises:
depositing a liner portion of the semiconductor layer at the first side of the stack of conductive layers and insulating layers; and depositing a bulk portion of the semiconductor layer at a side of the liner portion of the semiconductor layer away from the stack of conductive layers and insulating layers.

9 . The method of claim 7 , further comprising:
forming a channel structure comprising a blocking insulating layer, a charge storage layer, a tunneling insulating layer, and a channel layer, wherein the channel structure extends through the stack of conductive layers and insulating layers in the first direction, and a portion of the channel structure extends through at least a portion of the initial stack of layers.

10 . The method of claim 9 , wherein the removing the initial stack of layers comprises:
removing a portion of the blocking insulating layer, a portion of the charge storage layer, and a portion of the tunneling insulating layer; and exposing a portion of the channel layer.

11 . The method of claim 10 , wherein the semiconductor layer is in contact with the portion of the channel layer.

12 . The method of claim 2 , further comprising:
forming an array of channel structures in a core region between the first GLS structure and the second GLS structure; forming a dummy channel structure in a staircase region between the first GLS structure and the second GLS structure; and forming a peripheral contact structure in a peripheral contact region located on a side of the first GLS structure and the second GLS structure in the second direction.

13 . The method of claim 12 , wherein the first isolation structure separates the array of channel structures into a first sub array and a second sub array.

14 . The method of claim 12 , further comprising:
forming a conductor layer, wherein a first portion of the conductor layer is located at a side of the semiconductor layer away from the stack of conductive layers and insulating layers, and a second portion of the conductor layer extends through the semiconductor layer and in contact with the peripheral contact structure.

15 . The method of claim 1 , wherein a first width of the first isolation structure between the first portion of the first conductive layer and the second portion of the first conductive layer is wider than a second width of the first isolation structure between a first portion of the semiconductor layer and a second portion of the semiconductor layer.

16 . The method of claim 1 , wherein the subset of the stack of conductive layers and insulating layers comprises the first conductive layer and at least a second conductive layer.

17 . The method of claim 1 , further comprising:
forming a first contact structure connected to the first portion of the first conductive layer; and forming a second contact structure connected to the second portion of the first conductive layer.

18 . The method of claim 1 , wherein the semiconductor layer comprises polysilicon.

19 . The method of claim 1 , further comprising:
forming a periphery structure closer to the second side than to the first side of the stack of conductive layers and insulating layers.

20 . The method of claim 19 , wherein the forming the periphery structure comprises:
forming a first circuit coupled to the first portion of the first conductive layer; and forming a second circuit coupled to the second portion of the first conductive layer.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wu Linchun
• Kong Cuicui
• Xia Zhiliang
• Huo Zongliang

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title