Semiconductor memory device and method of manufacturing semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2026075823-A1
Application number	US-202519391455-A
Country	US
Kind code	A1
Filing date	Nov 17, 2025
Priority date	Aug 20, 2021
Publication date	Mar 12, 2026
Grant date	—

Abstract

A semiconductor memory device includes a discharge contact passing through a source structure, a gate stack disposed on a partial region of the source structure, a vertical structure passing through the gate stack, and an insulating pattern passing through the source structure between the vertical structure and the discharge contact.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a lower source layer including a gate overlap region and an extension region, the extension region extending from the gate overlap region; forming a sacrificial layer over the lower source layer; forming a discharge contact passing through the lower source layer within the extension region and the sacrificial layer; forming an insulating pattern passing through the lower source layer and the sacrificial layer between the lower source layer within the gate overlap region and the discharge contact; forming a gate stack including a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked over the sacrificial layer, and penetrated by a slit; and replacing a portion of the sacrificial layer overlapped by the gate stack with a doped semiconductor layer through the slit.

2 . The method of claim 1 , wherein the sacrificial layer is in contact with one sidewall of the insulating pattern, and
the doped semiconductor layer is in contact with another sidewall of the insulating pattern.

3 . The method of claim 1 , wherein the slit is formed at a distance spaced apart from the insulating pattern.

4 . The method of claim 1 , wherein the discharge contact directly contacts the lower source layer.

5 . The method of claim 1 , wherein the insulating pattern and the sacrificial layer are located between the doped semiconductor layer and the discharge contact.

6 . The method of claim 1 , wherein the insulating pattern has a sidewall in contact with the doped semiconductor layer and a sidewall in contact with the sacrificial layer.

7 . The method of claim 1 , the method further comprising:
forming a lower structure that includes a substate having a discharge impurity region, a lower insulating structure covering the substrate, and a discharge interconnection connected to the discharge impurity region; and forming an upper source layer over the sacrificial layer, wherein the lower source layer is formed over the lower structure, wherein the insulating pattern passes through the upper source layer, wherein the discharge contact passes through the upper source layer and extends to be in contact with the discharge interconnection, wherein the gate stack is formed over the upper source layer.

8 . The method of claim 7 , wherein the doped semiconductor layer includes an impurity of a conductivity different that of the discharge impurity region.

9 . The method of claim 7 ,
wherein the doped semiconductor layer includes an n-type impurity, and wherein the discharge impurity region includes a p-type impurity.

10 . The method of claim 7 , wherein the forming of the gate stack comprises:
alternately stacking the plurality of interlayer insulating layers and a plurality of material layers over the upper source layer; forming a preliminary cell plug that passes through the plurality of interlayer insulating layers, the plurality of material layers, the upper source layer, and the sacrificial layer and extends into the lower source layer within the gate overlap region; forming an upper slit the passes through the plurality of interlayer insulating layers and the plurality of material layers; and replacing the plurality of material layers with the plurality of conductive patterns through the upper slit.

11 . The method of claim 10 , wherein the upper slit is disposed at a distance from the insulating pattern.

12 . The method of claim 10 , the method further comprising:
forming a spacer insulating layer on a sidewall of the upper slit; and forming a lower slit that passes through the upper source layer, wherein the slit is formed by connecting the upper silt and the lower slit.

13 . The method of claim 10 , wherein the doped semiconductor layer is in contact with the upper source layer and lower source layer.

14 . The method of claim 1 , the method further comprising:
forming a channel hole that passes through the gate stack and the sacrificial layer and extends into the lower source layer within the gate overlap region; forming a memory layer along a surface of the channel hole; and forming a channel layer along a surface of the memory layer.

15 . The method of claim 14 , wherein the replacing of the portion of the sacrificial layer with the doped semiconductor layer comprises:
removing the portion of the sacrificial layer overlapped by the gate stack; removing a portion of the memory layer between the lower source layer and the gate stack; and filling a region from which the portion of the sacrificial layer and the portion of the memory layer are removed with the doped semiconductor layer.

16 . The method of claim 15 , wherein the doped semiconductor layer is in contact with a portion of the channel layer between the lower source layer and the gate stack.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Taek
• Jung Hye Yeong

Classifications

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10B43/30

  characterised by the memory core region · CPC title