Semiconductor structure

Patent metadata

Field	Value
Publication number	US-2026075799-A1
Application number	US-202519253113-A
Country	US
Kind code	A1
Filing date	Jun 27, 2025
Priority date	Sep 10, 2024
Publication date	Mar 12, 2026
Grant date	—

Abstract

Embodiments of the present disclosure provide a semiconductor structure, including multiple rows of first word lines and multiple first conductive lines. Each of the first conductive lines is provided in correspondence with and connected to each of the first word lines in odd-numbered rows or even-numbered rows; multiple first conductive contacts are each provided in correspondence with each of the first conductive lines, and multiple second conductive contacts are each provided in correspondence with and isolated from each of the first conductive contacts; and each of the second conductive contacts is connected to each of the first contact pads. The semiconductor structure in the embodiments of the present disclosure has a simpler interconnection manner, which simplifies a process flow while increasing signal density.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a first memory cell array, the first memory cell array comprising a plurality of rows of first word lines extending in a first direction, and the first word lines being isolated from each other; a first interconnection region comprising a plurality of first conductive lines extending in the first direction, each of the first conductive lines being provided in correspondence with and connected to each of the first word lines in odd-numbered rows or even-numbered rows; a first conductive contact combination, the first conductive contact combination being disposed in the first interconnection region, the first conductive contact combination comprising a plurality of first conductive contacts, each of the first conductive contacts being provided in correspondence with each of the first conductive lines, and each of the first conductive contacts extending in a second direction and being connected to each of the first conductive lines; and a second interconnection region, the second interconnection region being disposed adjacent to the first memory cell array and the first interconnection region in the first direction, a second conductive contact combination being provided in the second interconnection region, the second conductive contact combination comprising a plurality of second conductive contacts, and each of the second conductive contacts being provided in correspondence with and isolated from each of the first conductive contacts; and a plurality of first contact pads being provided in the second interconnection region, each of the second conductive contacts extending in the second direction and being connected to each of the first contact pads, wherein there is a minimum distance D 0 between adjacent first conductive contacts in the first direction, there is a minimum distance D 1 between adjacent second conductive contacts in the first direction, and the minimum distance D 0 is less than the minimum distance D 1 ; and in the second direction, each of the first conductive contacts has a minimum length L 0 , each of the second conductive contacts has a minimum length L 1 , and the minimum length L 0 is less than the minimum length L 1 .

2 . The semiconductor structure according to claim 1 , wherein in the first direction, the first conductive contacts in the first conductive contact combination have an average width W 0 , the second conductive contacts in the second conductive contact combination have an average width W 1 , and the average width W 0 of the first conductive contacts is less than the average width W 1 of the second conductive contacts.

3 . The semiconductor structure according to claim 1 , wherein the first conductive contact combination comprises a first column of first conductive contact combination and a second column of first conductive contact combination that are spaced apart in a third direction, the first conductive contacts in the first column of first conductive contact combination are respectively connected to the first conductive lines in odd-numbered rows, and the first conductive contacts in the second column of first conductive contact combination are respectively connected to the first conductive lines in even-numbered rows; in the first direction, at least one first conductive contact in the first column of first conductive contact combination and a corresponding second conductive contact in the second conductive contact combination have a maximum distance D 2 therebetween; and a first conductive contact and a second conductive contact that have the maximum distance D 2 therebetween form a first baseline row, and a maximum distance between each of the first conductive contacts in the second column of first conductive contact combination disposed adjacent to the first baseline row and each of the second conductive contacts provided corresponding thereto is less than the maximum distance D 2 .

4 . The semiconductor structure according to claim 3 , wherein the first conductive contacts and the second conductive contacts that are disposed adjacent to the first baseline row form a first reference row and a second reference row respectively; there is a maximum distance D 3 between a first conductive contact and a second conductive contact in the first reference row, and there is a maximum distance D 4 between a first conductive contact and a second conductive contact in the second reference row; and the maximum distance D 3 is greater than the maximum distance D 4 , and both the maximum distance D 3 and the maximum distance D 4 are less than the maximum distance D 2 .

5 . The semiconductor structure according to claim 3 , wherein in the first direction, at least one first conductive contact in the second column of first conductive contact combination and a corresponding second conductive contact in the second conductive contact combination have a maximum distance D 5 therebetween; and a first conductive contact and a second conductive contact that have the maximum distance D 5 therebetween form a second baseline row, and a maximum distance between each of the first conductive contacts in the first column of first conductive contact combination disposed adjacent to the second baseline row and each of the second conductive contacts provided corresponding thereto is less than the maximum distance D 5 .

6 . The semiconductor structure according to claim 5 , wherein the first conductive contacts and the second conductive contacts that are disposed adjacent to the second baseline row form a third reference row and a fourth reference row respectively; there is a maximum distance D 6 between a first conductive contact and a second conductive contact in the third reference row, and there is a maximum distance D 7 between a first conductive contact and a second conductive contact in the fourth reference row; and the maximum distance D 6 is greater than the maximum distance D 7 , and both the maximum distance D 6 and the maximum distance D 7 are less than the maximum distance D 5 .

7 . The semiconductor structure according to claim 1 , wherein the first memory cell array further comprises:
a plurality of columns of first bit lines extending in a third direction, the first bit lines being isolated from each other; a third interconnection region, the third interconnection region comprising a plurality of second conductive lines extending in the third direction, and each of the second conductive lines being provided in correspondence with and connected to each of the first bit lines in odd-numbered columns or even-numbered columns; a fourth interconnection region, the fourth interconnection region being disposed adjacent to the first memory cell array and the third interconnection region in the third direction, some of the second conductive lines being disposed in the third interconnection region, and some of the second conductive lines extending from the third interconnection region to the fourth interconnection region; and a third conductive contact combination, the third conductive contact combination comprising a plurality of third conductive contacts, the third conductive contacts comprising a plurality of third conductive contacts disposed in the third interconnection region and a plurality of third conductive contacts disposed in the fourth interconnection region, and each of the third conductive contacts being correspondingly connected to each of the first conductive lines; and a fourth conductive contact combination being provided in the third interconnection region, the fourth conductive contact combination comprising a plurality of fourth conductive contacts, and each of the fourth conductive contacts being provided in correspondence with and connected to each of

Assignees

• Cxmt Corp

Inventors

• Bai Shijie
• Sheng Bohui
• Rao Depeng

Classifications

• H10B12/485

  Bit line contacts · CPC title

• H10B12/488

  Word lines · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title