Semiconductor package

Patent metadata

Field	Value
Publication number	US-2026053052-A1
Application number	US-202519059485-A
Country	US
Kind code	A1
Filing date	Feb 21, 2025
Priority date	Aug 14, 2024
Publication date	Feb 19, 2026
Grant date	—

Abstract

A semiconductor package includes a base chip including a semiconductor body and a through-electrode structure penetrating through the semiconductor body and having a protrusion portion protruding upwardly of the semiconductor body, an insulating pattern on a side surface and an upper surface of the base chip, a chip stack on the base chip and the insulating pattern, and an encapsulant on the insulating pattern and covering at least a portion of the chip stack. The insulating pattern includes a first insulating portion on a side surface of the semiconductor body, and a second insulating portion on an upper surface of the semiconductor body and covering a side surface of the protrusion portion of the through-electrode structure. The insulating pattern includes an inorganic insulating material, and the encapsulant includes an organic insulating material.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a base chip including,
a semiconductor body, and
a through-electrode structure penetrating through the semiconductor body, the through-electrode structure having a protrusion portion protruding upwardly of the semiconductor body;
an insulating pattern on a side surface and an upper surface of the base chip; a chip stack on the base chip and the insulating pattern; and an encapsulant on the insulating pattern and covering at least a portion of the chip stack, wherein the insulating pattern includes,
a first insulating portion on a side surface of the semiconductor body, and
a second insulating portion on an upper surface of the semiconductor body, the second insulating portion covering a side surface of the protrusion portion of the through-electrode structure,
the insulating pattern includes an inorganic insulating material, and the encapsulant includes an organic insulating material.

2 . The semiconductor package of claim 1 , wherein the insulating pattern has a structure in which the first insulating portion and the second insulating portion are integrally connected.

3 . The semiconductor package of claim 1 , further comprising:
an upper pad on the through-electrode structure, wherein the second insulating portion vertically separates the upper pad and the semiconductor body.

4 . The semiconductor package of claim 1 , wherein
the base chip includes a logic chip, and the chip stack includes at least one memory chip.

5 . The semiconductor package of claim 1 , wherein
the insulating pattern includes silicon nitride (SiN), and the encapsulant includes an Epoxy Molding Compound (EMC).

6 . The semiconductor package of claim 1 , wherein, when viewed from above, at least a portion of an upper surface of the first insulating portion is at a lower level than an upper surface of the second insulating portion.

7 . The semiconductor package of claim 1 , wherein the encapsulant includes
a first lower end in a first region, the first region vertically overlapping the semiconductor body, and a second lower end at a lower level than the first lower end in a second region, the second region not vertically overlapping the semiconductor body.

8 . The semiconductor package of claim 1 , further comprising:
a lower pad on a lower surface of the base chip; and a lower protective layer below the lower surface of the base chip and a lower surface of the insulating pattern, the lower protective layer surrounding at least a portion of the lower pad.

9 . The semiconductor package of claim 8 , wherein the lower protective layer comprises silicon nitride (SiN).

10 . The semiconductor package of claim 1 , wherein the chip stack includes,
a plurality of first semiconductor chips stacked on the base chip; and a second semiconductor chip stacked on the plurality of first semiconductor chips, wherein a thickness of the second semiconductor chip is greater than or equal to a thickness of each of the plurality of first semiconductor chips.

11 . The semiconductor package of claim 1 , wherein the base chip has a width greater than a width of the chip stack in a direction parallel to the upper surface of the base chip.

12 . The semiconductor package of claim 3 , further comprising:
a bump structure on the upper pad; and an adhesive layer surrounding at least a portion of each of the upper pad and the bump structure.

13 . A semiconductor package comprising:
a base chip including,
a semiconductor body, and
a through-electrode structure penetrating through the semiconductor body, the through-electrode structure having a protrusion portion protruding upwardly of the semiconductor body;
an insulating pattern on a side surface and an upper surface of the base chip; a chip stack on the base chip and the insulating pattern; and an encapsulant on the insulating pattern and surrounding at least a portion of the chip stack, wherein the through-electrode structure includes,
a via plug,
a barrier layer surrounding a side surface of the via plug, and
an insulating spacer layer surrounding a side surface of the barrier layer, and
the insulating pattern and the encapsulant include different materials from each other.

14 . The semiconductor package of claim 13 , wherein the insulating pattern covers the upper surface of the semiconductor body and surrounds a side surface of the protrusion portion of the through-electrode structure.

15 . The semiconductor package of claim 13 , wherein an upper surface of the via plug is coplanar with an upper surface of the insulating pattern.

16 . The semiconductor package of claim 15 , wherein an upper surface of the insulating spacer layer is coplanar with the upper surface of the insulating pattern.

17 . The semiconductor package of claim 13 , further comprising:
an upper pad on the through-electrode structure and the insulating pattern, wherein a lower surface of the upper pad is in contact with an upper surface of the through-electrode structure and an upper surface of the insulating pattern.

18 . The semiconductor package of claim 13 , further comprising:
a buffer insulating layer between the insulating pattern and the semiconductor body.

19 . The semiconductor package of claim 18 , wherein the buffer insulating layer includes a first portion extending between a side surface of the protrusion portion of the through-electrode structure and the insulating pattern and a second portion extending between the insulating pattern and the semiconductor body.

20 . A semiconductor package comprising:
a base chip; a chip stack on the base chip, the chip stack including a plurality of first semiconductor chips stacked in a vertical direction; an insulating pattern including a first insulating portion and a second insulating portion, the first insulating portion being on a side surface of the base chip, the second insulating portion connected to the first portion and extending between the base chip and the chip stack; and an encapsulant on the insulating pattern, the encapsulant covering at least a portion of a side surface of the chip stack and contacting the insulating pattern, the encapsulant including a material different from a material of the insulating pattern, wherein the base chip is spaced from the encapsulant by the insulating pattern, a side surface of the insulating pattern and a side surface of the encapsulant are vertically aligned, and at least a portion of the first insulating portion has an upper surface at a level lower than an upper surface of the second insulating portion.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Juil
• Kim Dongjun
• Kim Hyunho
• Park Hyungjun
• Jeong Kwangok
• Jung Jaemok

Classifications

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W74/473

  containing a filler · CPC title

• H10W74/481

  comprising semiconductor materials · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title